Flash Memory Boot

[kevin239955_st]

Posted on January 29, 2015 at 13:56

Hi

Section 6.1.1 of the SPC560x Reference Manual says that ''in order to successfully boot from flash memory, you must program two 32-bit fields into one of 5 possible boot blocks.''

I have written 0x005A005A to address 0x00000000 accordingly (on our SPC56B Discovery Kit) but neglected to program a valid 32-bit reset vector. Now the board is stuck in reset (I can't even connect the JTAG probe).

Is there any way of resolving this? Not just to ''unbrick'' the development hardware but if this were to happen ''in the field''.

Thanks

Kevin

[kevin239955_st]

Posted on March 18, 2015 at 15:27

Ok I give up. There's a write to a pad configuration register (0xC3F90084) that isn't taking effect unless I connect the debugger. Presumably UDE bypasses some memory protection settings (as mentioned when i ''restart program'' via the debugger it then works). What do I set to enable this write? 

Thanks

Kevin

[Erwan YVIN]

Posted on March 18, 2015 at 17:04

Hello Kevin ,

You try to configure PC[0] :

PC[0:1] are available as JTAG pins (TDI and TDO respectively).

 

PH[9:10] are available as JTAG pins (TCK and TMS respectively).

 

If the user configures these JTAG pins in GPIO mode the device is no longer compliant with IEEE 1149.1-2001.

This pin is not configurable by the Pinmap Wizard.

You can try by the manual iosettings.

Best regards

                     Erwan

[kevin239955_st]

Posted on March 18, 2015 at 18:18

I'm trying to configure PC[2] and PC[3], which are connected to the User LEDs on the SPC560B Discovery Board. These are configured by PCR34 (0xC3F90084) and PCR35 (0xC3F90086) respectively.

Kevin

[kevin239955_st]

Posted on March 23, 2015 at 14:45

I've tested another build and this affects UART as well. I'm guessing that the Pad Configuration Registers are read-only until something else is set up. Should we be in a particular mode (e.g. DRUN, RUN0) to set these? Advice please.

Thanks

Kevin

*EDIT* Resolved this by setting ME_MCTL and ME_RUN_PC0 to enable peripherals in DRUN mode.