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AYazı.3
Associate II
May 17, 2022
Solved

I configured 86 slot one cycle , but configurable message buffer number of the first message buffer segment and second buffer segment are total 32 . So do i read/write all slots in cycle despite message buffer number is 32?

  • May 17, 2022
  • 5 replies
  • 3008 views

I am currently developing a Flexray driver. I cant understand a few point. This message buffer configurable like that : "configure each message buffer by setting the configuration values in the Section 21.5.2.65: Message Buffer Configuration, Control, Status Registers (MBCCSRn), Section 21.5.2.66: Message Buffer Cycle Counter Filter Registers (MBCCFRn), Section 21.5.2.67: Message Buffer Frame ID Registers (MBFIDRn), Section 21.5.2.68: Message Buffer Index Registers (MBIDXRn)" . There is 32 message buffer that i can configure slot number , cycle number. So is there any misunderstand , or i can read/write just 32 slot?

    This topic has been closed for replies.
    Best answer by Didier_G

    Hello,

    SPC56xL70 has 64 Message Buffers.

    These should cover your static and dynamic slots allocation. Depending on your

    Flexray topology, you may need to reconfigure some MBs on the fly depending on

    where you are in the communication cycle, among the cycles (64) and among the

    MT (common value is 5000MT per cycle). The IP embeds 2 timers that may help you to know where

    you are, or you may poll FR_MTCTR and FR_CYCCTR. Refer to “Individual Message

    Buffer Reconfiguration�? in the RM for details.

    Depending on the performance or the number of slots involved, some FR topologies may not be achieved within 64 MBs.

    “Message Buffer Cycle Counter Filtering�? is also available to smoothen the bandwidth required (you may transmit every 2, 4, 8, 16, 32 or 64 cycles and reconfigure in-between).

    FIFOs are there to smoothen CPU load too.

    Note: you need to be familiar with FlexRay Communications System Protocol Specification, Version 2.1 Rev A.

    Thanks.

    5 replies

    ODOUV.1
    ST Employee
    May 17, 2022

    Hello,

    I suppose you still working on SPC56xL70 so the reference manual is RM0342

    you can see in Table 327. FlexRay memory map (Sheet 1 of 4):

    there are not 32 but 64 slots of these registers MBCCSR/MBCCFR/MBFIDR/MBIDRX

    Best regards.

    AYazı.3
    AYazı.3Author
    Associate II
    May 17, 2022

    ok , i assume there is 64 message buffer , but still there is not enough buffer for all slots , is there?

    ODOUV.1
    ST Employee
    May 17, 2022

    Concerning the number of buffers, the document is clear:

    0693W00000Nq7EBQAZ.pngthere are 64, no more

    concerning the slots, what are you talking about ?

    BRs

    AYazı.3
    AYazı.3Author
    Associate II
    May 17, 2022

    Thank you for your kindly response . I understood Message Buffer Frame ID Registers (MBFIDRn) as a slot releated parameter in one cycle(For example assigned message buffer frame id 2 , it is filter for slot number 2 messages ). Am i wrong ?

    ODOUV.1
    ST Employee
    May 17, 2022

    You are right, the FID in MBFIDRn is 11 bits

    so it looks like we can identify up to 2048 different frames to filter them

    but as we have only 64 of these registers, we can filter only 64 among the 2048 at a time.

    may you will have to reconfigure them dynamically ?

    I will try to find an expert to provide a better answer but as I told you last week we did not implement this FlexRay driver example for SPC5Studio, so I may not find the answer...

    Best regards

    Didier_G
    Didier_GBest answer
    ST Employee
    May 17, 2022

    Hello,

    SPC56xL70 has 64 Message Buffers.

    These should cover your static and dynamic slots allocation. Depending on your

    Flexray topology, you may need to reconfigure some MBs on the fly depending on

    where you are in the communication cycle, among the cycles (64) and among the

    MT (common value is 5000MT per cycle). The IP embeds 2 timers that may help you to know where

    you are, or you may poll FR_MTCTR and FR_CYCCTR. Refer to “Individual Message

    Buffer Reconfiguration�? in the RM for details.

    Depending on the performance or the number of slots involved, some FR topologies may not be achieved within 64 MBs.

    “Message Buffer Cycle Counter Filtering�? is also available to smoothen the bandwidth required (you may transmit every 2, 4, 8, 16, 32 or 64 cycles and reconfigure in-between).

    FIFOs are there to smoothen CPU load too.

    Note: you need to be familiar with FlexRay Communications System Protocol Specification, Version 2.1 Rev A.

    Thanks.