INTC HW vector mode

[aurelien23]

Posted on November 17, 2016 at 12:15

Hello e2e,

Is there any exemple demonstrating the INTC HW vector mode? I'm using SPC564B74 and I don't know how to add my vectors in the linker script. I added .extern pit1_ISR in ivor.s:

/*

 * INTC registers address.

 */

.equ  INTC_IACKR, 0xfff48010

.equ  INTC_EOIR,  0xfff48018

.extern pit1_ISR

but I was getting the assembler error:

../bsp/components/spc56ecxx_osal_component/lib/src/ivor.s:49: error: unrecognized external symbol type '''' must be STT_OBJECT/STT_FUNC

So I removed it since the manual says that extern is ignored. It compiles then but the PIT is not generating interrupts...

My goal is to use FlexCAN, LINFlex and PIT1 using HW vector mode to be as fast as possible.

By the way, I'm following SPC5Studio since V2, and with V5, I have to say that it has never been so easy to start from scratch! (especially the license setup since node locked detection is just a click away) Thanks a lot!

#intc

[Erwan YVIN]

Posted on November 21, 2016 at 11:44

Hello Aurelien ,

Did you solve your issue ?

B74 Hardware Vector Mode is managed by the IVPR

cf chapter 

HVEN should be set to 1

cf chapter 19.4.2 in RF

Best regards

Erwan

[Erwan YVIN]

Posted on November 23, 2016 at 11:18

Hello Aurelien ,

Here is the feedback of a SPC5x Expert,

''First of all, the documentation about hardware interrupts is unclear and could confuse the reader

With an unclear documentation I did a simple test by enabling hardware interrupts (HVEN = 1)

and using PIT0 as source of interrupt.

As soon as a PIT0 interrupt is fired the Program Counter (PC) is set to 0x000018EC where:

• 0x8EC is the PIT0 offset
• 0x1000 is the vector table offset

In order to manage the (hardware) interrupt in hardware mode, at address 0x000018EC need to have a branch ('bl') instruction

which redirect the execution flow to the user interrupt handler.

The user interrupt handles will be responsible to acknowledge the interrupt source and to return to normal

execution (using an ‘rfi’ instruction at the end).

For each hardware interrupt, in the hardware vector table, 4 bytes available (see table 155 in Reference manual)

At the end, the vector table should be a list of branch instructions and the vector table must be

placed (by a linker script directive) to a specific address (0x00001000 in case of Bolero)''

Best regards

Erwan

[aurelien23]

Posted on November 24, 2016 at 09:25

Hello Erwan,

these precisions will help for sure. Thank you.

Happy to discover that this community forum will be updated!

Aurélien

[Erwan YVIN]

Posted on November 24, 2016 at 09:49

Hello Aurelien ,

Long time that i am waiting for this migration. (Sharepoint)

All the posts will be migrated.

We will switch on Jive 5th december.

    Best Regards

Erwan