Is it possible to disable 8x division for system clock?

[AZayt.5]

Hello,

I am bringing up an SPC570S50E1. Using the dev kit I am able to successfully bring up and run some simple code, but I observe a clock division for the clock going into the core.

When I route out clockout with a divider of zero and sysclk running from the crystal, I observe a 40 MHz oscillation on the clockout pin. However, when I write assembly code that toggles a GPIO pin every clock cycle, I observe that the clock cycles take 200 ns each, suggesting a 8x clock division happening between the clock stage that the clockout feeds from and the clock stage that the processor core feeds from. (If I run the core from the internal 16 MHz oscillator, I observe the same division behavior). I cannot find any registers or configuration bits in the manual that describe such an 8x clock division. Please let me know if this 8x division is inherent or if there is some way to disable it, so that each clock cycle indeed takes 25 ns. 

Thank you very much,

Anton

[Erwan YVIN]

Hello Anton ,

Do you use SPC5Studio test application ?

in the clocktree component there are some clock dividers

Best Regards

Erwan

[AZayt.5]

Hello Erwan,

Thank you for your prompt response. Unfortunately, changing these settings does not affect the processor speed division I observe. I understand that the processor feeds from CGM_SC_DC0 and that divider value is already at 1 (no division). The 40MHz clockout (when CGM_SC_DC2 divider is also 1) suggests that the sys clock should also be running at 40 MHz, but I observe a 5 MHz processor speed.

The attached image is from page 446 of the manual describing the clock tree for the SPC570. Two elements exist between clockout and sysclk: CGM_SC_DC0 (which is set to divide by 1) and the grey box labeled "PC FS". I cannot find mention of that box in the manual anywhere. Is it possibly a 8x divider? Would it be possible to clarify what PC FS is?

Thank you very much for your time,

Anton