SPC56 5V Tolerant Logic Levels

[Matthew Richardson]

Posted on June 11, 2018 at 10:15

I feel like I am not finding an explicit answer to this question in the errata.  I notice that the SPC56 has a 5V tolerant ADC, but I am wondering if I can use 5VDC logic for the GPIO pins?  I have some legacy 5V shift registers and I am wondering if the GPIO inputs are 5V safe...

[Erwan YVIN]

Posted on June 11, 2018 at 11:47

Hello Matthew ,

you can find some useful information in the datasheet for SPC56EL70

http://www.st.com/content/ccc/resource/technical/document/datasheet/7a/58/72/a0/1c/45/4a/1b/DM00070691.pdf/files/DM00070691.pdf/jcr:content/translations/en.DM00070691.pdf

 

  Best regards

                  Erwan

[Matthew Richardson]

Posted on June 11, 2018 at 20:22

I don't feel like that data sheet is explicit.  I understand that the ADC pins are 5 Volt tolerant when the ADC Reference is 5V, but I guess this is mostly for ADC register conversion reasons, not hardware?.  ADC pads are multiplexed with GPIO.  This leads me to believe that maybe the hardware is tolerant, at least prior to mux.  Based on how vague the datasheet is, it wouldn't be wise for me to assume that any of the GPIO is 5 Volt tolerant, even if the pin is tolerant when configured for ADC.  I'm not using any ADC, and I understand that there is a difference between accepted logic levels, verse actual hardware tolerance.  Is there a more definitive answer, are GPIO input pins 5 Volt TTL tolerant?

VDD_HV_ADR    max is 6.4V

VDD_HV_IO        max is 4.5V <- this serves as an input reference and output current source (i think).

GPIO [Input]        max is ?