SPC564B70 (Bolero) Power Draw in Standby Mode

[mark239955_st]

Posted on May 23, 2014 at 19:21

Can anybody offer any knowledge of using STANDBY mode? 

I am putting the chip in STANDBY and it appears to go there, as the processor goes dormant until I cause a wakeup event.  But the current draw on the VDD_LV power-input (2.1v) is ridiculously high (~100ma).   I've confirmed that the power is not going out the ports - those are all ok - it appears to be going to core/peripherals (hence VDD_LV). 

Following the spec carefully, with weeks of scrutiny and experimentation.   Can give more details if anybody has experience here...

tnx,

-mark

#powerconsumption-power-standby

[Erwan YVIN]

Posted on May 27, 2014 at 10:58

Hello Mark ,

sorry for our late answer.

you can check in the chapter : (cf reference manual of SPC564B70 (Bolero))

Table 88. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) Field Descriptions

Peripheral control during STANDBY

0 Peripheral is frozen with clock gated

1 Peripheral is active

And your peripheral control registers are maybe badly configured.

   Best regards

                Erwan YVIN