SPC56EL - using FlexPWM DMA functionality

[Patriks]

Posted on May 13, 2015 at 10:58

Hello,

I would like to reload PWM duty cycle every 10 PWM periods using DMA functionality. Therefore I configured FlexPWM subodule 0 and DMA channel An array stores 8 different values for VAL3 register which equal duty cycles from 10%...80%.

My DMA channel step looks like that:

DMAMUX.CHCONFIG[10].R = DMA_CHANNEL_ENABLED | DMA_CHANNEL_NTRIGGERED | 12;

edmaChannelSetup(10,&dcPWM[0],&mcPWM_A.

SUBMOD

[0].

VAL_3

.

R

,2,0,1,1,2,8,-16,0,0);

Now VAL_3 register is written by DMA, but always with the last table element. If I reduce the DMA iterations to 4, then VAL_3 always gets the value of 4th element from my table.I already used DMA for reloading eTimer compare values and had no problems with writing one element from a table to compare registers with each compare event.

Is thereno way to use the next element from table with every reload event? Additionally, I am not quitesure if I understand the reload feature with DMA. The DMAEN register include the VALDE bit. In the reference manual, the description says ''This read/write bit enables DMA write requests for the VALx register when RF is set''. Does it mean that I get one request per VAL register (means totally six) or should the request be used to write all VAL registers with one DMA channel? Best regards, Patrik

[Patriks]

Posted on May 18, 2015 at 08:37

Hello,

Two additional questions regarding my issue: 

    - Do I have to set the LDOK bit manually if I update VALx registers with DMA?

    - What about the EXT_FORCE signal? I didn´t find a pin with that function.

Best regards,

Patrik

[Erwan YVIN]

Posted on May 28, 2015 at 15:06 Hello Patrik , You are usingenhanced direct memory access(eDMA) with DMA Channel enabled

with triggering

. 1) According to the RM ''• 16 independently selectable DMA channels routers – the first 4 channels additionally provide a trigger functionality'' You have to use the first 4 channels 2) i do not see any allocation of edma Channel (edmaChannelAllocate)

/**
* @brief EDMA channel allocation.
*
* @param[in] ccfg channel configuration
* @return The channel number.
* @retval EDMA_ERROR if the channel cannot be allocated.
*
* @special
*/
edma_channel_t edmaChannelAllocate(

const

edma_channel_config_t *ccfg) {
 /* If the channel is already taken then an error is returned.*/
 if (channels[ccfg->dma_channel] != NULL)
 return EDMA_ERROR; /* Already taken. */

#if SPC5_EDMA_HAS_MU
X /* Programming the MUX.(DMA Channel enabled with triggering)*/
 SPC5_DMAMUX.CHCONFIG[ccfg->dma_channel].R = (uint8_t)(0x80 |
 ccfg->dma_periph);
#endif /* !SPC5_EDMA_HAS_MUX */

3) The reload feature should be triggered by PIT. To set DMAEN is not sufficient. At the end you should launch edmaChannelStart it updates , DMA Set Enable Request Register. For ADC & DSPI , there are some example how to use eDMA. Patrik , do you have an example of your application ? you can send to me directly your application by email. Best regards Erwan

[Erwan YVIN]

Posted on May 28, 2015 at 15:25

Hello Patrik ,

    - Do I have to set the LDOK bit manually if I update VALx registers with DMA?

yes ...

1) you have to set CLDOK - Clear Load Okay

2) update VALx registers , 

3) force the reload of Registers ValueLDOK - Load OK

    - What about the EXT_FORCE signal? I didn´t find a pin with that function. 

I am checking with PWM Experts.

 

              Best regards

                       Erwan

[Patriks]

Posted on June 08, 2015 at 15:17

Hello Erwan,

Ok, now that point is clear to me. Means that I have to set LDOK manually after changing the VALx registers by DMA.

Only open question is the EXT_FORCE signal. In reference manual chapter14, CTU interaction on page 285 shows that the EXT_FORCE signal for FlexPWM_0 could be eTimer output channel 1. I already tried this interaction and it works well. But I found no solution to use an external signal for as described in 26.2.5

Best regards,

Patrik

[dangelo.giuseppe-sst]

Posted on September 30, 2015 at 11:09

Hello Patrick,

an external signal can be connected to the FlexPWM EXT_FORCE input using the eTimer_0.CH1 in PULSE-OUTPUT Mode. If the counter is setup for CNTMODE = 001, with the OFLAG OUTMODE set to ‘11111’ (gated clock output) and the ONCE bit not set, the counter will output a pulse stream of pulses that has the same frequency of the selected clock source. The selected clock source can be an external signal, for example, on the eTimer_0.CH0 which is used as input for eTimer_0.CH1.

Best regards,

Giuseppe