SPC56EL60L3- flash array integrity check

[alessandro2]

Posted on May 22, 2017 at 11:43

Hello, I'm working with SPC56EL60L3 and SPC5STUDIO v5.0.

I need to implement flash array integrity check,as part of the power on self test procedure.

I got some sample code from ST application engineering, but I can't get it to work.

The odd thing is that, if I try to run the code in debug mode, it works.. When I try to run it outside of the debig mode, I get an unhandled exception.

Please find my code below (I made some little changes to the code provided by ST application engineer).

/* flash array integrity test */

#define PAR_CFLASH_MISR0 0xBFC5FC60

#define PAR_CFLASH_MISR1 0x2D32A870

#define PAR_CFLASH_MISR2 0xDAF09F36

#define PAR_CFLASH_MISR3 0xC0DB86FF

#define PAR_CFLASH_MISR4 0x00016014

#define FLASH_PSW 0xF9F99999

#define UT0_UTE 0x80000000U

#define UT0_AID 0x00000001U

#define UT0_AIE 0x00000002U

#define UT0_AIS 0x00000004U

static int32_t CoreFlashIntegrityTest( void )

{

int32_t retVal_i32 = CORE_TEST_ERROR;

int8_t misrErrCounter_i8 = 0;

CFLASH.UT0.R = FLASH_PSW;

while( ( CFLASH.UT0.R & UT0_UTE ) == 0);

CFLASH.HBS.R = 0x000003FF;

CFLASH.UT0.R &= ~( UT0_AIS ); /* Default value is zero*/

/* Seed the MISR UM0 thru UM4 with desired values.*/

CFLASH.UMISR[0].R = 0U;

CFLASH.UMISR[1].R = 0U;

CFLASH.UMISR[2].R = 0U;

CFLASH.UMISR[3].R = 0U;

CFLASH.UMISR[4].R = 0U;

/* Array Integrity Enable */

CFLASH.UT0.R |= UT0_AIE;

while( ( CFLASH.UT0.R & UT0_AID ) == 0 );

misrErrCounter_i8 += REGS_COMP( CFLASH.UMISR[0].R, PAR_CFLASH_MISR0 );

misrErrCounter_i8 += REGS_COMP( CFLASH.UMISR[1].R, PAR_CFLASH_MISR1 );

misrErrCounter_i8 += REGS_COMP( CFLASH.UMISR[2].R, PAR_CFLASH_MISR2 );

misrErrCounter_i8 += REGS_COMP( CFLASH.UMISR[3].R, PAR_CFLASH_MISR3 );

misrErrCounter_i8 += REGS_COMP( CFLASH.UMISR[4].R, PAR_CFLASH_MISR4 );

CFLASH.UT0.R &= ~( UT0_AIE );

if ( misrErrCounter_i8 == 0 )

{

retVal_i32 = CORE_TEST_OK;

}

return retVal_i32;

}

Furthermore I have the following questions:

- HBS setting: how do I configure HBS. It looks like it's used for selecting the flash sectors on which I want to run the test. How do I relate the desired sector to the register value?

- In the sample code the MISR[0:4[ registers are initialized to 0. Why is that? Is 0, always the right value?

- In the sample code, the MISR[0:4] registers are compared to some expected values at the end of the test. How do I determine the expected values? Are those fixed values?

Thank you.

Regards

Alessandro

[alessandro2]

Posted on May 23, 2017 at 09:59

Hello, 

in the sample code provided by ST, I noticed a directive which made me think the flash integrity routine may need to be run from RAM:

#pragma ghs section text='.ram_code'

This is placed at the beginning of the function.

At the end of the function I found this:

#pragma ghs section text='default'

So, now there is another question: do I need to run this code from RAM? 

Thank you.

Regards

Alessandro

[GPrad]

Posted on May 23, 2017 at 15:55

Hello Alessandro,

Yes, that code must run from RAM:

During an array integrity sequence, the Flash memory array ignores any incoming read requests. When a Flash array integrity check is in progress, the Flash memory controller terminates all Flash access requests with an error.

Regards

[alessandro2]

Posted on May 26, 2017 at 15:09

Hello Mosè,

thank you for your reply.

So now the problem is: how do Iget that piece of code running from RAM? (I posted a specific question, since this looks like a more general topic, not necessarily linked to flash array integrity test).

Regards

Alessandro

[GPrad]

Posted on May 23, 2017 at 16:32

Hello Alessandro,

HBS register functions are shown in TABLE 287 of Leopard Reference Manual.

MISR register is described in Table 292. UM0 field descriptions of Leopard reference manual.

   The MISR can be seeded to any value by writing the MISR registers.

   A the end of the AIC, MISR[0:4] registers are compared to the expected values that depend on the selected sectors and their content.

Regards

[alessandro2]

Posted on June 12, 2017 at 09:55

Hello Mosè,

thank you for your reply.

HBS and LMS registers are described in the user manual (table 293 describes the LMS register and table 294 describes HBS).

My application is using sectors 2,3,4 (L2, L3 and L4 of low address space) and 6 (M0 of the medium address space) of the flash memory.

So i configued the registers as follows:

CFLASH.HBS.R = 0x00000000; /* none of the sectors in high address space is used */

CFLASH.LMS.R = 0x0001001C; /*L2, L3, L4 and M0 are used */

Is this correct? 

One more question is related to the MISR registers functionality..

I read table 299 in section 24.1.5.12.1, but I still don't get how it works..

The question is: how do I determine the expected value to be compared to the content of the MISR registers after the integrity check?

In my code, the MISR registers are initialized to 0, before running the test.

Thank you.

Regards.

Alessandro

[GPrad]

Posted on June 14, 2017 at 09:42

Hello Alessandro,

According to your description CFLASH.LMS.R set is correct.

You can follow an 'empiric' method to find the expected values of the signature after array integrity check:

Flash the micro, run the array integrity check, at the end of the calculation (without any error)  the MISR registers will contain the value you search for.

If the content of L2, L3, L4 and M0 sectors won't change, you can use this value as the expected one.

Best regards,

Mosè