SPC56EL60L5CBF Exceptions

[dariusz]

Posted on July 06, 2015 at 09:16

Hello,

I have a few questions regarding exceptions in microcontroller mentioned in the topic.

I'm trying to cause Illegal instruction exception (IVOR6) by substituting part of hex with 0x0000. According to PowerISA v2.06B ''an instruction consisting entirely of binaly 0s is illegal, and is quaranteed to be illegal in all future versions of this architecture''. The problem is no exception is taken. From what i know this exception is not maskable so it always should be taken assuming requirements are met. I also tried writing program counter to memory region consisting of all 0s and no exception is taken. Is this behaviour correct and how can I cause this exception?

How can i translate hex code to instructions performed by microcontroller, hex code doesn't seem to correspond to opcodes presented in e200z4 core documentation?

When exacly are Floating-point unavailable (IVOR7) and SPE Unavailable (IVOR32) exceptions taken? If MSR[FP] = 0 and MSR[SPE] = 0 and division of floating-point is performed by execution of efsdiv operation, no exception is taken. Is this behaviour correct?

Best regards

[Erwan YVIN]

Posted on July 08, 2015 at 13:51

Hello Dariusz ,

SPC56EL60L5CBF has well a Signal Processing Engine.

1) About Illegal Exception (IVOR6), Yes , ''An instruction is consisting entirely of binary 0s is illegal''

it should be illegal and IVOR6 should be handled. Anyway, I am cross-checking with experts why IVOR6 is not handled.

2) about HexCode , Did you check Appendix A in PowerISA V2.06B

the last bits efsdiv should be 2C9

in my case , it matches between my HEX code and the appendix A

(Test done with SPC5Studio)

3)

*)For the e200, the floating point unit is not supported in hardware, and an unimplemented

operation exception will be generated for attempted execution of Power ISA embedded

category floating point instructions when FP is set (not IVOR7)

*)MSR[SPE] is defined as the SPE/EFPU available bit.

if  MSR[SPE] = 0 and division of floating-point is performed by execution of efsdiv operation, the exception should not be happened. The behavior is correct ;) 

cf Chapter 5.7.18 :

''The SPE unavailable exception is taken if MSR[SPE] is cleared and execution of an SPE instruction other

than the scalar floating-point instructions (efsxxx) or brinc is attempted, or execution of a EFPU evfsxx

instruction is attempted.''

Best regards

                      Erwan

[dariusz]

Posted on July 09, 2015 at 11:09

Hello,

1) Would be grateful for information what you found out.

2) I'm using Trace32 and Lauterbach debugger in case this matters. Let's consider lwz (Load Word & Zero) operation. In software i found 3 occurences of this operation:

C007    se_lwz    r0, 0x0(r7)

opcode  target   source

1100 00|00 000|0 0111

0x30      0x0      0x7        - 0x30 is lfs (load floating-point single)

50E836E0    e_lwz    r7, 0x36E0(r8)

opcode  target   source   argument

0101 00|00 111|0 1000| 0011 0110 1110 0000

0x14      0x7      0x8       0x36E0        - 0x14 is rlwimi (rotate left word immed then mask insert)

514836E0    e_lwz    r10, 0x36E0(r8) 

0101 00|01 010|0 1000| 0011 0110 1110 0000

0x14      0xA      0x8       0x36E0

Help me understand this. According to e200z4 core and Power ISA documentation opcode for lwz operation should be 100000 (0x32). Am i missing something or am i just plain stupid :]

Thank you very much for your help

Best regards

[Erwan YVIN]

Posted on July 10, 2015 at 12:05

Hello Darius ,

1)  we are continuing to investigate

2) it matches well , your opcode calculation is just not good. (Cf Below)

Cf APPENDIX A

se_lwz

C007  se_lwz    r0, 0x0(r7) ==> SD4 C000---- VLE se_lwz Load Word and Zero Short Form

1100 00|00 000|0 0111

0x30      0x0      0x7        - 0x30 is lfs (load floating-point single)

1100 0000 | 0000 0111

0xC007

50E836E0    e_lwz    r7, 0x36E0(r8) ==> D 50000000 VLE e_lwz Load Word and Zero

514836E0    e_lwz    r10, 0x36E0(r8) ==> D 50000000 VLE e_lwz Load Word and Zero 

    Best Regards

               Erwan

[dariusz]

Posted on August 26, 2015 at 11:45

Hello,

Any results on the investigation why Illegal Exception is not called?

[Erwan YVIN]

Posted on August 27, 2015 at 12:01

Hello Dariusz ,

Could you give your MSR Configuration when SE_ILLEGAL is taking acccount like a NOP ?

se_illegal is used to request an illegal instruction exception. A program interrupt is generated. The contents

 

of the MSR are copied into SRR1 and the address of the se_illegal instruction is placed into SRR0.

 

MSR[WE,EE,PR,IS,DS,FP,FE0,FE1] are cleared.

   Best Regards

               Erwan