Clock division and duty cycle for ST8034P

[FGrie.3]

In the Data Sheet for the ST8034P the following is not clear about the ST8034PQR

• when the CLK output is active, does fCLK = fCLKIN or fCLK = fCLKIN/2 ?
• assuming fCLK = fCLKIN: is there some duty cycle (or other characteristic) to be met on the CLKIN input in order to get the specified 45/55% duty cycle on the CLK output?

Context is migrating a design from ST8034ATDT to ST8034PQR. The old design uses the fXTAL/2 functionality of table 13, with CLKDIV=1. ST8034P has no CLKDIV input. But it's untold if the behavior is that of CLKDIV=1 or CLKDIV=0.

A clue that fCLK = fCLKIN is that both have the same maximum frequency (26 MHz). But then, I wonder how the 45/55% duty cycle for CLK in table 8 is obtained without some slightly tighter duty cycle spec on CLKIN.