CSn low to positive edge SCLK in low power mode state?
Hi there!
In the S2-LP datasheet it is stated that the typical delay is 40 us:
Does this mean that the host microcontroller must use a CSn low delay of at least 40 us when the S2-LP is in STANDBY or SLEEP mode and it wants to send an SPI command to put the S2-LP into the READY mode?
What is the consequence if a delay of 3 us is used? Must this delay of 40 us be respected on all SPI commands until the S2-LP is in READY state?
Thanks in advance,
Pieter
