ST87M01 Power Sequencing: V_IO (3.3V) vs V_PMU (2.5V) Start-up

[AndreasC]

I am designing a board with the ST87M01. I am using two separate LDOs (TLV757 series) both connected in parallel to a 5V VBUS source.

Rail A: 3.3V for GPIO/UART.

Rail B: 2.5V for the Modem PMU.

Since both LDOs start simultaneously, there may be a slight millisecond variation in when each rail reaches its target voltage.

Questions:

1. Does the ST87M01 have a strict requirement for the 2.5V PMU rail to be stable before 3.3V appears on the GPIO pins?
2. Is there a risk of latch-up or back-powering if the 3.3V rail rises ~100µs faster than the 2.5V rail?
3. Should I implement a hardware delay (e.g., RC delay or Power-Good signal) on the 3.3V LDO Enable pin to ensure it trails the 2.5V rail?

PS. add ST87M01 label to choose in forum for topic creation. 

Greetings,

Andreas

[Didier HERROUIN]

Dear AndreasC,

There is no constraint on the sequencing of power supplies.

And no risk of latch-up with a VIO=3.3V.

Concerning the label, thanks for your input, a "ST87 series" label has been created.

Best regards,

Didier