VN9D30Q100F SPI communication SPI error, Chip reset bit

[han.1]

now i trying spi communication using VN9D30Q100F(slave) with NXP's S32K148(master).

i set VN9D30Q100F to normal mode.

after than, i checked output pwm pulse through six channels.

when i read output status register(address is 0x20h to 0x25h) of VN9D30Q100F, always spi error and reset bit is set.

but, in global status byte, any errors doesn't occurred. exactly global status byte's spi error bit and reset bit not set at same time(in one cycle of 24bit SPI communication).

i want to know the reason of error bit setting in output status register.