Skip to main content
Visitor II
January 30, 2026
Question

MOSFETs Q1, Q2, Q9, Q10 damaged when applying 230 VAC input with STGAP2SICS gate drivers

  • January 30, 2026
  • 2 replies
  • 177 views

Problem Summary

We have developed a three‑phase servo motor drive using STGAP2SICS isolated gate drivers and IPW65R190C7XKSA1 MOSFETs.

The inverter works perfectly at low DC input voltage (25–40 V DC).
However, when we apply 230 V AC (rectified ~320 V DC) and send control signals to the U, V, W inputs, MOSFETs Q1, Q2, Q9, and Q10 fail immediately, even under no‑load condition.


Motor Specifications

  • Voltage: 230 V
  • Power: 2000 W
  • Rated RPM: 2200
  • Gearbox Ratio: 5.067:1

Test Conditions

Parameter Low Voltage Test High Voltage Test
Input Source25–40 V DC230 V AC (rectified)
Output Frequency10 Hz36 Hz
Modulation Index0.50.5
Measured Current~2 A7–9 A (unexpected, no load)
Dead‑time300 ns300 ns
Start MethodInstant StartRamp‑up

Gate Driver IC Used

STGAP2SICSNTR


Symptoms

  • Only the U‑phase high‑side and low‑side MOSFETs fail (Q1, Q2).
  • Same issue happens in the W‑phase (Q9, Q10).
  • MOSFETs fail instantly as soon as the PWM is applied at high‑voltage input.
  • No load connected to the motor during testing.

Attachments

  • Full schematic PDF
  • Firmware settings (PWM configuration, dead‑time, carrier frequency, etc.)

Request for Help

We would like help in diagnosing why MOSFETs fail only at high voltage.
Specific guidance needed on:

  1. STGAP2SICS gate driver configuration

    • Proper BOOT strap design
    • Recommended gate resistors (turn‑ON / turn‑OFF)
    • DESAT protection setup
    • Miller clamp usage
  2. PCB layout concerns

    • Gate loop inductance
    • Power ground vs isolated ground separation
    • High‑side switching node dv/dt handling
  3. Firmware‑related issues

    • PWM edges
    • Dead‑time sufficiency at high voltage
    • Shoot‑through analysis
  4. Whether the unexpectedly high 7–9 A no‑load current indicates:

    • Incorrect switching sequence
    • MOSFET cross‑conduction
    • dv/dt‑induced gate turn‑ON
    • Faulty bootstrap supply design

Any insights from ST engineers or community experts will be greatly appreciated.

Thank you!

2 replies

Peter BENSCH
Technical Moderator
January 30, 2026

Welcome @Nithi, to the community!

Is there a specific reason why you are using a driver for SiC MOSFETs for Si MOSFETs?

Perhaps you should consider the p2p replacement STGAP2HS instead?

Regards
/Peter

AScha.3
Super User
January 30, 2026

>STGAP2SICS gate driver configuration

AScha3_0-1769780963823.png

1. I hope you have no 0,1u there !  NO cap here.

2. gate resistors: i would start with value from ds : 10 + 10 ohm 

3. remove D1 . (what should it do useful ?? )

4. with new mosfet ... :)  , no HV power supply + load : check with dual channel scope the gate signals !

looks like this:

AScha3_1-1769781660505.png

(for this test connect scope probes + ground to hi+lo gate + source ; without any supply on HV !!!)

 

IF they look fine, remove probes,  try with HV (30V or so) ; if good , = almost zero supply current , apply some load.

IF all fine, try with full HV .

 

"If you feel a post has answered your question, please click ""Accept as Solution""."