STGAP2D Interlock

[STH]

Hello,

I have a problem with STGAP2D and the interlock pin.

If the interlock pin is on GND, SD and Brake are high, INB is high and the INA is high for 1s after this time 10ms low, than again 1s high and again 10ms low and so on.

The output A is only low and the output B is 1s low and the 10ms high.

But in the datasheet is written, if the interlock pin is on GND, INA and INB are high, than the outputs also are high.

Can anyone tell me, what is wrong?

I need this funktion.

Thank you and best regards

Stefan

[Peter BENSCH]

Welcome @STH, to the community!

Please do not be confused: the pin iLOCK interlock has the function to enable/disable interlock. This is shown again in table 9 of the data sheet, where the line with the text Interlocking refers to the activated function. As soon as iLOCK is connected to GND, interlocking is disabled, which is why both outputs may be H (usually unwanted in half-bridge applications).

So if you need an active interlock, you should set iLOCK to H.

Hope that helps?

Regards
/Peter

[STH]

Hello Peter,

thank you for reply.

I have the iLock switched to GND, but Interlock is still active. The inputs are high but outputs are low. 

Regards

Stefan

[Peter BENSCH]

Interesting behaviour that does not correspond to the specification and should be clarified with your distributor or directly with Online Support OLS.

Regards
/Peter