HSO ADC config

[propu]

Hi :

[VERSION]: MCSDK 6.3.1

I have some questions regarding the HSO ADC sampling configuration. I am currently using a custom PCB to validate the HSO algorithm with the STM32G431 chip. ADC1 and ADC2 are used to sample voltage and current separately. The sampling configuration is as follows: ADC1 performs four samples for current U, current W, voltage U, and temperature. ADC2 performs four samples for current V, voltage V, voltage W, and bus voltage. After reading the HSO Start-up document, I noticed that the Ksample delay parameter is affected by the sampling order. I am unsure whether my ADC configuration is correct. If it is correct, my switching frequency is currently 16k. What should the Ksample delay be? Should I modify the ADC1 sampling to current U/V/W/temperature and the ADC2 sampling to voltage U/V/W/bus voltage?

[Gael A]

Hello propu,

While using HSO, you want all 3 of your current samplings to be done as close to each other as possible, and same thing for voltages. This means your first guess is correct, with two ADCs, sampling should be done the following way :
ADC1    ADC2
Curr 1    Curr 2
Curr 3    Volt 1
Volt 2     Volt 3
VBUS  /  Temp

Concerning the Ksampledelay, the method is the same for 3-ADC and 2-ADC sampling. Your Ksampledelay is the time between your current and voltage sensing, scaled to duty cycle. Looking at the sampling order, there is roughly 1.32 * ADC sampling time between your currents sampling and your voltages sampling (that value is 1 if you use 3-ADC sampling, 1.32 comes from the mean of the 3 samplings that are not done exactly at the same time). Your Ksampledelay is thus 1.32 * ADC_Sampling_Time * PWM_Frequency.

[propu]

Hi Gael A:

  Thank you for your timely reply。

Currently, I have the following configuration. The ADC clock is derived by dividing the PLL clock, and the final frequency of the ADC is 42.5 MHz. The configured sampling hold time is 6.5 cycles. Assuming the total conversion time is 16.5 cycles, the ADC sampling time should be 1/42.5 MHz * 16.5 = 0.38 µs. The PWM frequency is 16000 Hz. If we calculate using 1.32 * ADC_Sampling_Time * PWM_Frequency, the value obtained for KSAMPLE_DELAY is 0.008199. Could you please check if this calculation is correct?

 

[z h]

The configured sampling hold time is 6.5 cycles. Assuming the total conversion time is 6.5+12.5=19 cycles?

1.32* 1/42500000 *19 * 16000 = 0.00944188235294117647058823529412

[propu]

yeah ,you are right.