STM32 MCUs Security

Dear,I am writing to inquire about the inclusion of a validity period in the debug authentication certificates used with the STM32H7S3 microcontroller.My project requires that the debug access certificates I provision have a limited, defined lifespan to align with security policies. I am currently using the latest versions of STM32TrustedPackageCreator (v2.20.0) and PSA_ADAC (v0.2.0) to generate these certificates.I have reviewed the documentation for both tools and have not found a user-configurable option to specify a notAfter (as is available for X.509) or expiration date for the generated ADAC certificates.Could someone please clarify the following:Is it possible to generate ARM ADAC certificates with a defined validity period using any publicly available tools?If not, is there a different process, tool, or service that would allow me to create such certificates?Are the certificates generated by the public tools created with a fixed, pre-defined validity pe

Hi,We are using SBSFU and FreeRTOS in STM32H755xI. We are planning to use Zephyr RTOS in STM32H755xI. Can I use SBSFU bootloader in Zephyr RTOS?--Muthukrishnan

Hello Support Team,for testing purposes i am using the H533NucleoBoard. I can load my firmware into the MCU and the firmware is running as expected. I want use the final product in ProductionState: closed.The problem is, the firmware isn't running any longer whe changing the productionState to closed. But I am able to switch back to ProductionState: open  via Regression.Following informations:Used Tools: Stm32CubeProgrammer V2.20.0STLink V3 FirmwareVersion: V3J16M8Following Settings:TZEN: C3 (disabled) (I don't want to use TrusZone enabled)BOOT_UBE: B4 (OEM-iRot UserFlash)NSBOOT_LOCK : C3SECBOOT_LOCK : 0Sequence:1. set product state: Provisioning2. start provisioning3. set product state: closedLogFile of Provisioning process:06:55:11:421 : reset ap 106:55:11:421 : Reset MCU06:55:11:422 : Reconnecting...06:55:11:422 : Disconnected06:55:11:422 : ST-LINK SN : 0019002A343351153736393406:55:11:423 : ST-LINK FW : V3J16M806:55:11:423 : Board : NUCLEO-H533RE06:55:11:423 : Voltage : 3.30V0

Hi everyone,I have a question regarding SFI Option Bytes for the STM32H753ZI (Nucleo-H753ZI).Question:Which option bytes should I pick, since there are a lot of different combinations available: 1. Generated by TrustedPackageCreator: FLASH_OPTSR_PRG,0x17DEBBF0 FLASH_PRAR_PRG1,0x0000000F FLASH_PRAR_PRG2,0x0000000F FLASH_SCAR_PRG1,0x81000200 FLASH_SCAR_PRG2,0x81000200 FLASH_WPSN_PRG1,0xFFFFFFFF FLASH_WPSN_PRG2,0xFFFFFFFF FLASH_BOOT7_PRG,0x08002400 RESERVED,0x24000810 2. STM32CubeExpansion_RSSe_V1.1.0\Option_Bytes_Template\STM32H7\OB_H742_H743_H753_H750_v3.1.0.csv: FLASH_OPTSR_PRG,0x17DEBBF0 FLASH_PRAR_PRG1,0x0000000F FLASH_PRAR_PRG2,0x0000000F FLASH_SCAR_PRG1,0x81000200 FLASH_SCAR_PRG2,0x81000200 FLASH_WPSN_PRG1,0xFFFFFFFF FLASH_WPSN_PRG2,0xFFFFFFFF FLASH_BOOT7_PRG,0x1FF00800 RESERVED,0x1FF00800 3. x-cube-sfi-v1-5-0\STM32CubeExpansion_SFI_v1.5.0\Projects\NUCLEO-H753ZI\Applications\SFI\OEM_SecureRoom\OptionBytes\ob.csv: FOPTSR_PRG,0x13DEAAF8 FPRAR_P

Dear STMicroelectronics Community members,I am currently evaluating STM32 microcontrollers for a project that requires strong cryptographic capabilities. Our goal is to implement hybrid encryption, meaning we need hardware support for both symmetric encryption (e.g., AES, DES/3DES) and asymmetric encryption (e.g., RSA, ECC, public key cryptography), along with hashing functions (SHA-1, SHA-2, SHA-3 if available).Specifically, I would like to request:A list of STM32 families and part numbers that include dedicated hardware accelerators for:Symmetric ciphers (AES, DES/TDES)Asymmetric ciphers (RSA, ECC, or other public key accelerators)Hash functions (SHA-1, SHA-224, SHA-256, SHA-3, etc.)Hardware Random Number Generator (TRNG)Clarification on which STM32 series provide a comprehensive cryptographic hardware suite suitable for hybrid encryption schemes (combining symmetric + asymmetric algorithms).Recommendations on the most suitable STM32

HiI am trying to perform a secure boot implementation in STM32F439ZIT6. The datasheet shows that, there is Hash, RNG, AECS and TDES. Can I perform secure boot functionality using only STM32F439ZIT6 without using any external chip and if so, are there any library files which contain functions to perform this secure boot operation and is there any application notes, example codes or videos I can refer to perform this functionality? Thanks and Regards@avbST 

Hello,I am working with Nucleo-STM32U385RG to implement the Root of Trust (Secure Boot) feature, following the wiki guide: https://wiki.st.com/stm32mcu/wiki/Security:How_to_start_with_OEMiRoT_on_STM32U3My test environment is STM32Cube_FW_U3_V1.2.0.During step-by-step testing, I faced two issues that I need help with:.(1) OEMiRoT_Boot build error (postbuild.bat)When I build OEMiRoT_Boot with EWARM IAR v9.32 + STM32U3 patch, the build finishes but throws an error during the postbuild.bat step.The wiki doesn’t explain anything about postbuild in this step.Still, I got a binary file, so I could continue the flow.https://wiki.st.com/stm32mcu/wiki/Security:How_to_start_with_OEMiRoT_on_STM32U3#OEMiRoT_Boot_firmware_compilationFor comparison, I also tried with STM32H5 OEMiRoT_Boot build, but I encountered a very similar error:  https://wiki.st.com/stm32mcu/wiki/Security:How_to_start_with_OEMiRoT_on_STM32H573_and_563%E2%80%93TrustZone_enabled#STM32CubeFW_provided_code_compilation&nbsp

Hello,I am trying to configure the secure memory in Secure Protection Bank 1 of options bytes section and for this I have followed the STM32 MOOC tutorial to understand the concept of using secure boot code. But I am facing issues as the base address for Bank 1 is expected be 0x08000000 as mentioned in STM32 G4 system memory protection document and also in tutorial whereas its showing as 0x00000000 Below is the screenshot from STMCube Programmer Option Byte settings from G474RE Board for your reference.I have also checked the similar settings with G071 board and I am able to get the base address as 0x08000000 as below and implement the secure boot code but unable to do in G474.Are there any other settings that I am missing out to configure in G474 to add the SEC_SIZE1 value?Can you please help me with this?Thanks 

 1.Does the STM32H743VIT6 microcontroller include a HASH peripheral that supports SHA-256 operations?I am planning to implement HMAC-SHA256 verification for my application, but I have not found clear documentation confirming the presence of a compatible HASH peripheral.2.If I implement HMAC-SHA256 purely through software, how much time will it take to compute the hash for 1MB of flash data?I would like to understand the performance implications of a software-based approach compared to using the hardware HASH peripheral. 

Hi Everybody,I posted a comment here https://community.st.com/t5/stm32-online-courses/stm32h5-secure-manager-course/bc-p/824487/highlight/true#M27 yesterday because I am trying following the online course and what is written in the wiki to start developing an application on the STM32H573VI using the secure manager.At the moment I am starting the development by using the nucleo board for H573 however, by following the wiki, the only project that could be used for deploying the solution is an handswritten example that does not use the CubeMx.If I try to follow the old documentation on the youtube videos, as explained in the link provided, I am unable to set the boot path correctly.At the moment I am a bit lost, should I build my project without the use of CubeMx in case of secure manager? Will it be added in the future? I am missing something straightforward? thank you in advanceAndrea

 I'm porting OEM ROT examples from STM32WBA65I-DK1 to STM32WBA63CUI7 and need guidance.Devices:- Target: STM32WBA63CUI7 (2MB flash, CSP17)- Source: STM32WBA65I-DK1 (2MB flash, UFBGA169)Questions:1. Device Support: Any known STM32WBA63xx definition gaps for OEM ROT?2. Package Differences: CSP17 vs UFBGA169 considerations for GPIO/clocks/security?3. Memory Layout: Any subtle differences despite identical 2MB dual-bank flash?4. Build Integration: Best way to add STM32WBA63xx to STM32CubeIDE projects?5. BSP: Need custom BSP or can adapt existing ones?Any insights or similar experiences appreciated!Thanks!

Hello everyone,I would like to update the STM32 remotely using ESP32. So the Idea is to transfer the signed image via Bluetooth and to store it firstly on the esp32, which will transfer it in the end via UART to the STM32.After that the secure boot on the stm32 must verify the image signature. I came across X-CUBE-SBSFU but I actually don't know how to use it in my case. Should I only use the Ymodem protocol ? Best regards

I'm trying to understand an issue I am having with chaining decryption, using the shared key out of the SAES and have distilled the problem to the following example:I am attempting to encrypt and decrypt large blocks of data (65536 bytes). I can encrypt and decrypt the entire block in one fell swoop with one call to Encrypt and one call to Decrypt. I can encrypt and decrypt the entire block in small chunks with repeated calls to Encrypt and Decrypt back to back (En, De, En, De, ...). However if I encrypt the entire block in chunks then decrypt the entire block in chunks (En, En, En, ... De, De De, ...), I get bad data as my decrypted text.I'm trying to understand what I am setting up incorrectly for the decrypted data to be bad. I'm using a STM32H7S78-DK board, although any STM32H7Sxxx could be used in this example. I am using a clean CRYP_SAES_SharedKey_Appli project. I have added the following code to the project. Any help on this problem would be greatly appreciated:uint8_t pla

Hello,I'm not sure if I understand the RDP regression mechanism described on STM32U0 reference manual (RM0503 rev4) correctly. My general understanding is that it's possible to go from RDP2 => RDP1 => RDP0 if the OEM keys are set - if they are not set (all 0's or all 1's) the effect of RDP2 is the same as on devices without RDP regression feature, so the debug port is fully closed and can't be opened anymore.My confusion comes from the following descriptions of the manual:RDP level 2 description on page 79 states that the CPU debug port is disabled under reset.The same description states:Once in level 2, it is no more possible to modify the read protection level.Note 1. on page 80:When the protection level 2 is active, the Debug port, the boot from RAM and the boot from system memory are disabled.Contrarily, OEM RDP lock mechanism description for OEM 1/2 on pages 81 & 82 states that it's possible to go from RDP2/1 to RDP0/1 and states that the keys must be written to the

Hi guys i am trying to use stm32cryptolib library's encryption function. the main problem i am facing when i am trying to call the  cmox_initialize function it is giving the error cmox_init.c:(.text+0x1a): undefined reference to `cmox_ll_init'collect2.exe: error: ld returned 1 exit statusmake: *** [makefile:64: crypto.elf] Error 1"make -j8 all" terminated with exit code 2. Build might be incomplete.but it is strange although i have included the include file to path under which it's .h comes. The other err which i am facing that is this function written below is not returning CMOX_HASH_SUCCESScmox_mac_retval_t ret_val = cmox_mac_compute(CMOX_HMAC_SHA256_ALGO, // Algorithmmessage, sizeof(message)-1, // Message and its length(const uint8_t *)key, strlen(key), // Key and its lengthNULL, 0, // No custom datahmac_bin, sizeof(hmac_bin), // Output tag and expected size&tag_len // Output tag length pointer);  

We are here trying to achieve the HMAC-SHA-125 generation.we are using the cryptolib-4.3.5 . the implementation is in PNG file( only the main and hmac computation is shown)we are not getting any compilation error but we are getting ERROR as program output . If we are commenting out the error checking if condition, we are getting something like :aee0ab2b6302b529b7873bac798718f3a17bce27a0c0906b3e299942b9262bff                                   but the actual output should be like:b2793ffb929310a28134164a5ef650bdeb422fb34233f493fe323a60fb.

Friends, hello, I encountered a problem with starting DWT with PRODUСT STATE = 72;I measure the time between pulses (white beam of the logic analyzer) by the EXTI5 interrupt input (falling edge of the signal), TIME_LONG_SENS = DWT->CYCCNT / (SystemCoreClock / 1000000); and then reset the counter DWT->CYCCNT = 0U; I measured the number of pulses on the generator and the number of interrupts on the input, they are equal. Then after a certain delay I control the microcontroller output to send a pulse (red and yellow beams of the logic analyzer).The problem is that after zeroing DWT in the PRODUСT STATE = 72 state,One output pulse is skipped.it does not always start and upon arrival of the next interrupt, the DWT->CYCCNT value is zero, and accordingly, the measured time is also zero.If I set PRODUСT STATE = ED, then this problem does not occur and the same code works correctly.Please tell me what my problem is and how to solve it?

This is a follow up to this post:https://community.st.com/t5/stm32-mcus-wireless/conflict-betwenn-pka-and-ble-after-pairing/m-p/76599?search-action-id=65799734948&search-result-uid=76599So if I understand correctly , After CPU2 BLE stack finished working with the PKA, it turns it off, so to enable it we should : // Re-enable PKA if disabled if ((PKA->CR & PKA_CR_EN) == 0) { PKA->CR |= PKA_CR_EN; } My question is how to Lock it or check its not currently Locked? I want to prevent any issues or races with BLE stack? 

According to Wikipedia The MODBUS uses the CRC-16-ANSI also known as CRC-16-IBM. ​The normal hexadecimal algebraic polynomial being 8005 and reversed A001Initial value: 65,535.​Example of frame in hexadecimal: 01 04 02 FF FF B8 80(CRC-16-ANSI calculation for the 5 bytes from 01 to FF  gives 80B8 which is transmitted least significant byte first).​I found some code that does the CRC16 with lookup tables, and it provides the same answer. So I believe the Wiki example is correct. ​Reading the RM0394 Reference manual it appears it is a pretty simple peripheral. Only a few registers to set up. ​CRC->DR is the data register.You write to this register and it holds the result. ​the CRC->IDR is not clear what it is used for. Looks like 8-bit memory. ​The CRC->INIT has a reset value of FFFFFFFF which is the sme as what I need. ​The Only register that is not clear is the CRC->CR register. Bit 0 loads the CRC->INIT register value into the CRC->D

Hi everyone,I tried Secure Firmware Install (SFI) with the Nucleo-H563ZI. The process failed, however my device is still accessible. By connecting to the device via Hot plug and Access port 1 I am able to see that the device is in "Provisioning" state.The option bytes are as follows:{ "deviceId" : 1156, "bitNameToValue" : { "PRODUCT_STATE" : 23, "BOR_LEV" : 0, "BORH_EN" : 0, "IO_VDD_HSLV" : 0, "IO_VDDIO2_HSLV" : 0, "IWDG_STOP" : 1, "IWDG_STDBY" : 1, "BOOT_UBE" : 195, "SWAP_BANK" : 0, "IWDG_SW" : 1, "NRST_STOP" : 1, "NRST_STDBY" : 1, "TZEN" : 180, "SRAM2_ECC" : 1, "SRAM3_ECC" : 1, "BKPRAM_ECC" : 1, "SRAM2_RST" : 1, "SRAM1_3_RST" : 1, "NSBOOTADD" : 524288, "NSBOOT_LOCK" : 195, "SECBOOT_LOCK" : 0, "SECBOOTADD" : 0, "SECWM1_STRT" : 0, "SECWM1_END" : 127, "WRPSGn1" : -1, "SECWM2_STRT" : 0, "SECWM2_END" : 127, "WRPSGn2" : -1, "LOCKBL" : 0, "EDATA1_EN" : 0, "EDATA1_STRT" : 0, "EDATA2_EN" : 0, "EDATA2_STRT" : 0, "HDP1_STRT" : 1, "HDP1_END" : 0, "HDP2_

Hi,I have a STM32u585 where SFI worked on first attempt. Then I did a factory reset , post that I am not able to get SFi working again at all. Is there a residual / stale state I need to clear to be able to do SFI again?We do not have any OEM Keys set.I did a mass chip erase, factory reset and power cycled before trying again. Verified option bytes look good (TZEN=0, RDP=0). I have attached logs of the failure. Any help appreciated!

Hi All,I am following the UM2262 document. I will add a screenshot. I enabled the ENABLE_IMAGE_STATE_HANDLING flag to enable rollback, but after updating UserApp.bin, the device continues to reset. I will add a debug log screenshot (it’s not jumping into the application). Please help me with any references for the rollback feature using the SBSFU package version 2.6.x.  Document image 1:Debug image 2:  Regards,Raju

Hi,I have SBSFU working with my HW, which has a STM32U585, with some (minor) modifications to the B-U585I-IOT02A example. I also have an application that I need to run with the secure bootloader (as the nonsecure app), developed by a wider team (lets call this our "user" app). This was developed to date without trustzone being enabled. I can get the user app to begin to boot with the secure bootloader (so signing, addressing, startup, etc. are all OK). However, the user app runs out of RAM before doing anything useful, so I need to assign more RAM to the nonsecure app. As far as I can see the U5 SBSFU example configures/assigns SRAM1 (192KB) to the nonsecure app, and SRAM2 (64KB) and part of SRAM3 (first 32KB) to the secure app. This leaves the remainder of SRAM3 (480KB) and SRAM4 (16KB) unassigned/unused. A couple of questions:Our secure app doesn't require much RAM (does very little other than configuring the trustzone controller and MPU and booting the nonsecure

Hello, I am using STM32F103c6 cortex-m3. I am using 100 micro controllers in various boards. In some around 10 micro controllers, I have seen a issue of option bytes getting corrupted. Even though I am writing 0xA5 to RDP to remove read protection while flashing, sometimes it makes memory read protected and few times it work properly. The remaining 90 MCUs works fine! Even the WRP also gets corrupted in those 10 MCUs. No where I am making Read protected in code, only write protection ! (Write protection is also removed at flashing by setting 0xA5 on RDP)Could it be because of power fluctuation? As we are doing few auto power interrupt tests!!What could be issue?I flashed the MCU multiple time which are misbehaving without running the code( just flashing with RDP 0xA5, sometimes it flashes, sometimes it gets read protected and doesnot Flash)!!Did the MCUs gone bad??

I am trying to run ECDH p384 operation on STM32H753.Using the STM32 Cryptolib 4.5.0, I get the CMOX_ECC_ERR_MEMORY_FAIL error during the operationI increased the stack size to the maximumI was able to run this using mbedTLS + hardware blocks like RNG, CRYP, CRC enabled. And it runs but the time for ECDH P384 is about 200ms (with 480mhs clock). I was hoping to achieve times in the order of tens of milliseconds as described here.What am I missing?https://wiki.st.com/stm32mcu/wiki/Security:STM32H7_Series:_Cryptographic_Library_Performance#tab=STM32H753