STM32H753 Flash CRC address limitations

[NPato]

Hi,

Although not specified in the reference manual it looks like the CRC process within the FLASH module (see section 4.3.12) has to have start and end addresses aligned to possibly the CRC_BURST size (I've only tried 128 byte bursts so far). If not aligned the same data contents produces different CRC results depending on the values before and after the data.

Some might say this is implied when described in the CRC paragraph but the HAL code does not check for it and the documentation for the address registers do not mention it (sections 4.9.20 and 4.9.21 plus those for bank 2).

This is a fairly important thing to know if you intend to compare the CRC that the STM FLASH module calculates with one that was calculated somewhere else.

Hope this info prevents someone else wasting an afternoon finding it out.

Nigel

[Tesla DeLorean]

https://community.st.com/s/question/0D50X0000At0Hwg/is-there-any-example-program-for-halflashexcomputecrc-function

>>Hope this info prevents someone else wasting an afternoon finding it out.

Wasted more than that trying to make the functionality/math work. Got crickets from ST

[Tesla DeLorean]

https://community.st.com/s/question/0D53W000009hwO4SAI So I can find it later..