Low qspi clock frequency in ExtMem_Boot

[DDi S.1]

I noticed that any example created with touchGfx for the STM32H750B-DK demo board uses the ExtMem_Boot bootLoader that uses a 400Mhz clock instead of 480Mhz, but the strangest thing is that it uses a QSPI clock of only 50Mhz, when from the memory datasheet it could reach 120Mhz.

[GaetanGodart]

Hello @DDi S.1 ,

 

Can you send me a screenshot or your ioc file.
When I create a project for STM32H750-DK with an example from TouchGFX Designer, my QSPI clock is not at 50Mhz. I use TouchGFX 4.25.0, what about you?

 

Regards,

[DDi S.1]

Hi Gaetan Thanks for your interest.

As you know in stm32H750 the application code resides in QSPI and is executed by QSPI. The bootloader (ExtMem_Boot) configures the speed of the qspi and then puts it in "memory mapped" mode.

Unfortunately "ExtMem_Boot" does not have a .ioc file

Even if the TouchGFX application (I use the latest version), has a .ioc file in which you can see a higher speed of the qspi, it does not matter because the application cannot change the speed of qspi. I hope I was clear.

Regards.

Domenico

[GaetanGodart]

Hello @DDi S.1 ,

 

Yes you are right, the extMem_boot is changing the frequency to a lower one but I believe we change it back to 480MHz after in Core/src/main.c :

void SystemClock_Config(void)
{
 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

 /** Supply configuration update enable
 */
 HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);

 /** Configure the main internal regulator output voltage
 */
 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);

 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}

 /** Initializes the RCC Oscillators according to the specified parameters
 * in the RCC_OscInitTypeDef structure.
 */
 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 RCC_OscInitStruct.PLL.PLLM = 5;
 RCC_OscInitStruct.PLL.PLLN = 192;
 RCC_OscInitStruct.PLL.PLLP = 2;
 RCC_OscInitStruct.PLL.PLLQ = 4;
 RCC_OscInitStruct.PLL.PLLR = 2;
 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
 RCC_OscInitStruct.PLL.PLLFRACN = 0;
 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 {
 Error_Handler();
 }

 /** Initializes the CPU, AHB and APB buses clocks
 */
 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
 RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
 RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
 RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
 RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
 RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;

 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
 {
 Error_Handler();
 }
}

Note PLLN set to 192, not 160.

 

Do you use the latest available TBS and the latest TouchGFX version? If you have an older TouchGFX version, you will only see the available TBS for that version so you might miss the very latest TBS version even if it looks like you are selected the latest TBS.

 

Also, this is an old TBS where we used to overwrite configuration through BSP which could benefit from some improvement, so you are right, it might be suboptimal.

 

Regards,

[DDi S.1]

Thanks for the reply Gaetan.

The biggest problem however is not so much the frequency of the main clock at 400Mhz, but the QSPI clock set to 50Mhz.

From the MT25QL512ABB8ESF-0SIT datasheet it says that in dual bank you can get to 90Mhz.

In a system where the firmware resides in QSPI, this can represent a bottleneck.

I also could not change this aspect in extMem_boot.

Do you have a solution?

Regards

Domenico

[GaetanGodart]

On my STM32H750-dk project, in STM32CubeMX, the sys clock is set to 480 MHz and the clock used for QSPI is set to 240 MHz.
If the extMem_boot sets the sys clock to 400 MHz, the clock for QSPI is set to 200 MHz.
Then you can modify that value with the prescaler.
In your case, it seems to be set to 3 because 200/(3+1) = 50.
But if you set the prescaler to 2, you get 200/(2+1) = 67 MHz, close enough if the max frequency is 90 MHz.

In my TBS, it is set to 2 (so 67 MHz clock, the comment is wrong):

 

Regards,

[Tesla DeLorean]

If you set up the MPU correctly it should be able to cache QPSI memory, so the speed disparity will be less of an issue. It's pulling from both memories. You can also copy code to SRAM, or SDRAM and run from there.

You could experiment with DTR/DDR modes, with different commands and dummy cycles

With a 240 MHz bus clock, and QSPI divider 2,  240/(2+1) = 80 MHz

The original H7 was 400 MHz, this expanded to 480 MHz later, and as I recall there are some LDO vs SMPS limitations, and VOS settings.

The H750 die still has 1MB of FLASH, only 128 KB is tested.