GPIO output speed register setting

[David_]

How to set GPIO output speed register (slow, medium, fast, very fast) in accordance to SPI and the slower I2C, clock speeds respectively?   The data sheet specify in rise/fall time. Is it correct that the register actually set drive current?

SPI clock at 6MHz is 83ns high and 83ns low.  Should we aim to make rise/fall time a "certain percentage" of 83ns?  If so, how much?

Part is STM32WLE5JCI6TR,

SPI bus has two external devices. Pin capacitance is about 5pF per device, presumably the MCU alos count as one, plus 5pF for PCB. That will be 20pF.  When putting a scope X10 passive probe will add 15pF.  Total 35pF. Still under the 50pF on data sheet. SPI clock about 6MHz.

I2C has one external device. Clock is 100 to 400kHz.

Many thanks

[TDK]

> How to set GPIO output speed register (slow, medium, fast, very fast) in accordance to SPI and the slower I2C, clock speeds respectively?

You can set them in the GPIO tab in CubeMX.

> Is it correct that the register actually set drive current?

Yes.

> Should we aim to make rise/fall time a "certain percentage" of 83ns?

Edges can't be tuned that well. You only have 4 settings. You should set it so that it meets the requirement, but not any higher. Use the datasheet to pick the speed which meets requirements. For 8 MHz, it's probably medium. For I2C speeds, it's almost certainly low. Using a higher speed typically isn't a problem, but it will introduce more noise in the system.

 

[David_]

AN4899 states SPI signal pin has schmitt trigger.  Presumably, a slower rise/fall signal will be read ok, without generating a lot of high and low when signal is passing slowly at threshold level.  Right?

[TDK]

Yes, the signal will be read correctly with any of those speeds as long as you're not exceeding the max frequency. The schmitt trigger has hysteresis. At any digital gpio speed setting, it's only going to flip state once per edge.

[LCE]

At least with the H7, I found that the I2C pins should be set to maximum speed, it seems that's due to the open drain IOs.

[David_]

Many thanks.  May I ask what pull up R, I2C clock speed in that case?  What are signal wiring lengths?  Was it a custom made PCB or bread board?

[LCE]

custom board, "mixed signal" system with high res audio

I2C1: on a bus to modules: 2 - 5 slaves, trace length ~250 mm, pull-ups 4k7, clock speed 50 kHz

I2C4: 1 slave only, trace length ~70 mm, pull-ups 10k,  clock speed 100 kHz

[David_]

Interesting to see slow speed 50kHz is getting critical.    Just double checked data sheet, they specified many timing parameters.   Rise and fall times have maximum and no value for minimum.

[TDK]

Using low speed here for I2C on all my STM32H7 boards. Never saw an issue.

[LCE]

> Using low speed here for I2C on all my STM32H7 boards. Never saw an issue.

That's what I started with, maybe there was something else, I will check again... next week!

It also didn't make any sense to me, so I thought that was something STM23-GPIO-open-drain-specific (what a word!).

[David_]

Data sheet says, "The GPIOs can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a
relaxed VOL/VOH).".   There is no time value in this spec.  May be it refers to continuous current rating before the pad heat up and burn. 

On switching, push pull pin may output more than 20mA to charge or discharge the load (capacitance of receiving chip plus pcb stray capacitance)

On I2C, open drian configuration, rise time is limited by the pull up resistor, 4k7 and 10k means around half a mA.  Fall time for signal driven by the MCU at that time, depends on speed setting (drive current or slew rate)