Automatic upgrade of STM32H7_ETH_Example_IDE1.6.1 LWIP/FREERTOS by STM32CubeMx V6.2.1/FW_H7_V1.9.0 to V6.6.1/FW_H7_V1.10.0 breaks the example.

[Johi]

I am able to run the example STM32H7_ETH_Example_IDE1.6.1 properly.

This is a basic LWIP/FREERTOS example implementing ping on fixed IP.

I recreated the example in minute detail in STM32CubeMX V6.6.1 FW_H71.10.0; it failed.

In the process of finding the culprit I let STM32CubeMX do the upgrade

V6.2.1->V6.6.1 and FW_H71.9.0->1.10.0 of the original demo automatically.

After the upgrade, the demo failed as well.

(I can rebuild the original demo and change the configuration without problems)

Should I check all modifications made by the upgrade or is there a better way to solve this?

Update: After configuration, the HAL_ETH_IRQHandler() is called with a fatal bus error (DMAErrorCode 0x1100))

[Pavel A.]

The H7 ETH driver (and related examples) undergone a breaking change since release 1.9.0.

After update to 1.10 or later, you can copy the previous driver files from Src/Legacy and Inc/Legacy to make older examples work. Or, if you want to use the new version, the updated examples are here: https://github.com/stm32-hotspot/STM32H7-LwIP-Examples

[Johi]

Thank you very much for the tip. I assumed the reworked ethernet driver, as it was announced some while ago, had something to do with it. I will further explore the code and, if there are relevant findings, provide feedback to the community.

[Johi]

Hello @Pavel A.​ 

I have been comparing the Git example You referenced and the older one I downloaded from the ST site..

As far as I can see, the MPU does not protect the Rx_PoolSection/RxArraySection in the new example but it does in the old one. Is protection no longer necessary or is there another mechanism providing cache coherency in the new example?

In detail:

The Rx_PoolSection/RxArraySection buffers were moved from 0x3000 0000 SRAM1 to 0x2400 0000 AXI SRAM. The MPU configuration in the new example seems not to contain references to the 0x2400 0000 area. Is there another mechanism providing cache coherency, is cache coherency no issue or did I overlook something?

(In attachment a detailed analysis, maybe I should start a new thread, I do not know what is best.)