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Ivan Slivin
Associate
June 2, 2021
Solved

Clock Configuration feature stuck (trying to find a solution in an endless cycle)

  • June 2, 2021
  • 4 replies
  • 3287 views

The only HCLK frequency possible is 40MHz (ofcourse i need higher freq)

Please help me resolve this.

Best answer by Ivan Slivin

I have solved it. The issue was: CubeMx could not find proper PLL setup for SDMMC and USB unit. I've made it manually.

4 replies

Khouloud OTHMAN
Technical Moderator
June 2, 2021

Hello @Ivan Slivin​ ,

First let me welcome you to the STM32 Community :smiling_face_with_smiling_eyes:

Thanks for having reported, but I'm unable to reproduce the issue from my side. I can increase the HCLK frequency without problems.

It will be more helpful to attach your .ioc file for further check.

Thanks in advance,

Khouloud.

Ivan Slivin
Associate
June 2, 2021

Hi Khouloud, Thank you for the prompt response. Please try my project (attached)

Ivan Slivin
Ivan SlivinAuthorBest answer
Associate
June 2, 2021

I have solved it. The issue was: CubeMx could not find proper PLL setup for SDMMC and USB unit. I've made it manually.

Khouloud OTHMAN
Technical Moderator
June 3, 2021

Hi @Ivan Slivin​ ,

Glad that your problem is resolved :smiling_face_with_smiling_eyes:

In fact, sometimes STM32CubeMX is not able to resolve automatically some clock issue specially for the somewhat complex clock tree as the case of STM32F746VGTx.

As you have already mentioned the endless search for solution is due to the fact that CubeMx could not find proper PLL setup for SDMMC and USB unit.

The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC need a frequency lower than or equal to 48 MHz to work correctly.

More details about clock configuration can be found in the STM32F74xxx Reference Manual.

Do not hesitate to raise any problem/ feedback.

Khouloud.

Visitor II
February 21, 2025

I have a similar issue with the clock speed needed for USB_OTG_FS at 48 MHz. I'm using an STM32F413ZHT Nucleo board. I have issues where USART1 is both disabled and displays a warning triangle and I2C3 is both disabled and is shown in red text. The System Core RCC mode and configuration reports that the Master clock output 1 conflicts with USB_OTG_FS Activate_SOF.  How should the Reset and clock control (RCC) to get a clean generate code with manually setting PLL48CLK Mux to 48, fix the USART1 warning and I2C3?

Thank you

Visitor II
February 21, 2025

I'm running STM32CubeMX version 6.11.1 and added the .ioc