Cortex system timer config bug?

[TDJ]

According to RM0456, section 11.4 RCC clock functional description, p. 482:

"The RCC feeds the Cortex system timer (SysTick) external clock with the AHB clock (HCLK) divided by eight, or LSE or LSI. The SysTick can work either with this clock or directly with the Cortex clock (HCLK), configurable in the SysTick control and status register."
However, the corresponding clock settings, at least for STM32U5A5 seem to make no impact. Regardless of what is set, the generated source code is exactly the same.

The SysTick source is controlled by RCC_CCIPR1.SYSTICKSEL register 

Figure 36. Clock tree for STM32U5 Series

RM0456 does not clearly explain where the related STCALIB register mentioned in section 22.2 is located and how to set SysTick to work directly with HCLK. RCC_CCIPR1.SYSTICKSEL register (section 11.8.46) allows only for three values:
00: HCLK/8 selected,
01: LSI selected,
10: LSE selected

I am puzzled. Probably those who tried to implement this CubeMX config function were unclear as well.

Please advise.

[Pavel A.]

IIRC this was a bug in the CubeMX/IDE for earlier products. The /8 divisor was not taken into account. Looks that  the systick selector mux is still not implemented in Cube for U5?

 

 

[Tesla DeLorean]

HCLK would come from the selection in the SYSTICK peripheral itself, not ST's circuit

SYST_CSR.CLKSOURCE

https://www.st.com/resource/en/programming_manual/pm0264-stm32-cortexm33-mcus-programming-manual-stmicroelectronics.pdf

CubeMX probably has some separate configuration of SysTick itself.

Sure it's unhelpful from a point-and-click point of view, but that comes with the territory