CubeMX disable DCache not working properly. BUG

[AAlis.23]

 

When DCache is disabled, CubeMX still generates this:

#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */

If you comment out this line, CubeMX will uncomment it, causing some peripherals to fail.Using 6.14 and the STM32H743 cpu.

[Souhaib MAZHOUD]

Hello @AAlis.23 

Actually, this is a normal behavior as the definition of __DCACHE_PRESENT is on stm32h743xx.h and it did not affect the user code. When enabling DCACHE in CubeMX SCB_EnableDCache() should be called in main.c.

BR,

Souhaib

[TDK]

> causing some peripherals to fail

Why do you think this line is the cause?

 

DCACHE is present whether or not you use it.

[AAlis.23]

As you can see, when f_mount is called, the driver calls the function SCB_CleanDCache_by_Addr, and when DCache is enabled, the system fails. If __DCACHE_PRESENT is commented out, this code is not executed, and everything works fine.

It doesn't matter if the issue comes from somewhere else; the point is that even when DCache is disabled in CubeMX, it keeps overwriting the stm32H743xx.h file and uncommenting the line #define __DCACHE_PRESENT 1U, always setting it to 1. When I manually comment out this line, DCache is effectively disabled, and everything works correctly.

I consider this a bug because if I configure CubeMX to disable DCache, but it reactivates the line and sets it to 1 again, it is clearly doing it wrong.

I suppose the issue comes from the fact that defining DCache as present is technically correct, as the CPU does have DCache. However, the problem is that a part of the code calls this function and allows the execution of code that shouldn't run. The root cause is probably in the FATFS driver, but in any case, all the code is generated by CubeMX.

 

 

 

__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
{
 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
 if ( dsize > 0 ) { 
 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
 
 __DSB();

 do {
 SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
 op_addr += __SCB_DCACHE_LINE_SIZE;
 op_size -= __SCB_DCACHE_LINE_SIZE;
 } while ( op_size > 0 );

 __DSB();
 __ISB();
 }
 #endif
}

 

 

 

 

 

 

[TDK]

Okay, now we're getting somewhere.

 

Yes, that's definitely a bug somewhere. It probably shouldn't be cleaning cache that isn't in use, but it definitely shouldn't be hard faulting.

Can you show what addr and dsize are when the function is entered?

 

[AAlis.23]

I'm not sure what you're referring to. The HardFault memory address is the one in the screenshot: 0x800819C. Do you want me to check something specific? If you tell me where to look, I'll send it to you.