STM32 maximum ADC frequency confusion

[CTord.1]

I am using a STM32H723zg board for a project and I must read analog signals so I am using one 16-bit ADC. Based on the datasheet of this microcontroller serie, the maximum ADC clock frequency is 50 MHz for BOOST = 11.

However when I am configuring the ADC clock frequency with the STM32CubeMX, the ADC clock is automatically set with 96 MHz with no error. I would like to know if this ADC clock frequency configuration (96 MHz) affects negatively to the performance of the ADC (noise or erros in measurements) and if this ADC clock frequency is actually used by the microcontroller or if the microcontroller automatically uses another frequency that does not exceed 50 MHz.

I didn't find anything very useful in the documentation related to this question.

[S.Ma]

going To ADC (MHz), the ADC usually has a clock prescaler to scale it down.

Probably you will use 96/2 = 48MHz then.

If you want exactly 50 MHz, you will either cranck up the source to 100MHz or use a different clock source (the shown multiplexer above).

[CTord.1]

Thank you for the answer, could you tell me where I can find the internal architecture of the ADC where is the prescaler?

[S.Ma]

It is in the reference manual, the whole clock tree and RCC for what goes to peripherals.

For each peripheral which has its own prescaler (Timer, SPI, ADC, etc...), it is in each respective peripheral chapter.

[Ghofrane GSOURI]

Hello @CTord.1​ 

First let me thank you for posting.

Please check the RM0468 paragraph 28.4.3 ADC clocks and Figure 230. ADC clock scheme for more details .

Thx

Ghofrane

[CTord.1]

Thanks for the answers. I reviewed the diagram in the reference manual:

The input clock is divided by 2 after the multiplexer. Hence, If I undestood correctly, with a prescaler=1 and setting 100 MHz in STM32CUBEMX, the input clock frequency will be divided by 2 after the multiplexer and the ADCs will use actually 50 MHz in this case. Is this reasoning correct? I think is what @S.Ma​ mentioned