Skip to main content
TThan
TThan
Associate III
June 18, 2025
Question

STM32CubeMX, Memory Management Tool, Possible Bug with Access Permission Settings

  • June 18, 2025
  • 1 reply
  • 257 views

Settings:

STM32CubeMX 6.14.1
STM32H573VI
STM32CubeIDE v1.18.1

I am not quite sure, but up to my understanding the Memory Managment Tool has a bug when it comes to the "Access Permissions" settings.

When RAM is set-up like this (Access Permission set to "RW by priviledged code only"):

TThan_0-1750236081176.png

It creates an initialization code for the GTZC1 that disables priviledge checking for the SRAM:

/**
 * @brief GTZC Initialization Function
 * @PAram None
 * @retval None
 */
static void MX_GTZC_Init(void)
{

 /* USER CODE BEGIN GTZC_Init 0 */

 /* USER CODE END GTZC_Init 0 */

 MPCBB_ConfigTypeDef MPCBB_Area_Desc = {0};

 /* USER CODE BEGIN GTZC_Init 1 */

 /* USER CODE END GTZC_Init 1 */
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[0] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[1] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[2] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[3] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[4] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[5] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[6] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[7] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[8] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[9] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[10] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[11] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[12] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[13] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[14] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[15] = 0x00000000;
 if (HAL_GTZC_MPCBB_ConfigMem(SRAM1_BASE, &MPCBB_Area_Desc) != HAL_OK)
 {
 Error_Handler();
 }
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[0] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[1] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[2] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[3] = 0x00000000;
 if (HAL_GTZC_MPCBB_ConfigMem(SRAM2_BASE, &MPCBB_Area_Desc) != HAL_OK)
 {
 Error_Handler();
 }
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[0] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[1] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[2] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[3] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[4] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[5] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[6] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[7] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[8] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[9] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[10] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[11] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[12] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[13] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[14] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[15] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[16] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[17] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[18] = 0x00000000;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[19] = 0x00000000;
 if (HAL_GTZC_MPCBB_ConfigMem(SRAM3_BASE, &MPCBB_Area_Desc) != HAL_OK)
 {
 Error_Handler();
 }
 /* USER CODE BEGIN GTZC_Init 2 */

 /* USER CODE END GTZC_Init 2 */

}

 

But when RAM is set-up like this (Access Permission set to "RW by any priviledge level"):

TThan_1-1750236271189.png

It creates an initialization code for the GTZC1 that enables priviledge checking for the SRAM:

/**
 * @brief GTZC Initialization Function
 * @PAram None
 * @retval None
 */
static void MX_GTZC_Init(void)
{

 /* USER CODE BEGIN GTZC_Init 0 */

 /* USER CODE END GTZC_Init 0 */

 MPCBB_ConfigTypeDef MPCBB_Area_Desc = {0};

 /* USER CODE BEGIN GTZC_Init 1 */

 /* USER CODE END GTZC_Init 1 */
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[0] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[1] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[2] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[3] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[4] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[5] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[6] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[7] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[8] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[9] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[10] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[11] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[12] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[13] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[14] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[15] = 0xFFFFFFFF;
 if (HAL_GTZC_MPCBB_ConfigMem(SRAM1_BASE, &MPCBB_Area_Desc) != HAL_OK)
 {
 Error_Handler();
 }
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[0] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[1] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[2] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[3] = 0xFFFFFFFF;
 if (HAL_GTZC_MPCBB_ConfigMem(SRAM2_BASE, &MPCBB_Area_Desc) != HAL_OK)
 {
 Error_Handler();
 }
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[0] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[1] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[2] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[3] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[4] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[5] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[6] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[7] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[8] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[9] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[10] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[11] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[12] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[13] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[14] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[15] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[16] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[17] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[18] = 0xFFFFFFFF;
 MPCBB_Area_Desc.AttributeConfig.MPCBB_PrivConfig_array[19] = 0xFFFFFFFF;
 if (HAL_GTZC_MPCBB_ConfigMem(SRAM3_BASE, &MPCBB_Area_Desc) != HAL_OK)
 {
 Error_Handler();
 }
 /* USER CODE BEGIN GTZC_Init 2 */

 /* USER CODE END GTZC_Init 2 */

}

Maybe I do not understand the intention behind this setting correctly, but in my optinion it should be exactly vice-versa.

This caused me some headaches while trying to find out why GPDMA1 was not able to write any data into the RAM. 

Best Regards

  Thomas

1 reply

Ghofrane GSOURI
Ghofrane GSOURI
Technical Moderator
June 18, 2025

Hello @TThan 

First let me thank you for posting.

I'm currently investigating this issue issue .

Could you please  provide your IOC.

I 'will get back to you asap.

THX

Ghofrane

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
Terms & ConditionsAccessibility statement