STM32G0B1x - setting message RAM offset for using two FDCAN ports

[PPate.1]

Hi,

I am using 2 FDCAN ports on my custom board with STM32G0B1x MCU. As per application note AN5348, I can set message RAM offset for second port. But I don't see this setting in STM32Cube MX.

As per reference manual, I got following details:

But I am not sure where to set start and end addresses.

Please help.

Thanks,

Pradeep

 

 

 

[PPate.1]

Hi,

Referring to 'FDCAN_HandleTypeDef' structure details, i got its member variable 'msgRam'. Using information given in reference manual, I did following settings in initialization code of both CAN ports:

FDCAN1 port:

hfdcan1.msgRam.StandardFilterSA = 0x0000;

hfdcan1.msgRam.ExtendedFilterSA = 0x0070;

hfdcan1.msgRam.RxFIFO0SA = 0x00B0;

hfdcan1.msgRam.RxFIFO1SA = 0x0188;

hfdcan1.msgRam.TxEventFIFOSA = 0x0260;

hfdcan1.msgRam.TxFIFOQSA = 0x0278;

 

FDCAN2 Port:

hfdcan2.msgRam.StandardFilterSA = 0x0350;

hfdcan2.msgRam.ExtendedFilterSA = 0x03C0;

hfdcan2.msgRam.RxFIFO0SA = 0x0400;

hfdcan2.msgRam.RxFIFO1SA = 0x04D8;

hfdcan2.msgRam.TxEventFIFOSA = 0x05B0;

hfdcan2.msgRam.TxFIFOQSA = 0x05C8;

 

Can anyone confirm if this is the way it can be done?

Thanks,

pradeep

[Mahmoud Ben Romdhane]

Hello @PPate.1 ,

First let me thank you for posting.

Your request is under investigation, and I will get back to you ASAP.

Thanks.

Mahmoud

[Mahmoud Ben Romdhane]

Hello @PPate.1 ,

Thank you for bringing this issue. 

It has been reported to STM32CubeMX development team.

Internal ticket number: 204224 (This is an internal tracking number and is not accessible or usable by customer)

Thanks.

Mahmoud

[ricky-fleet]

Hello @Mahmoud Ben Romdhane , I know this is marked resolved, but we are running into the same issue on STM32CubeMX v6.16.0 for a project using an STM32H723VGTx. There is no place in the GUI to input the MessageRAMOffset and the generated functions do not include an appropriate offset, so it appears this is still an outstanding issue, at least for the H7 processor family.

void MX_FDCAN1_Init(void) {
 /* USER CODE BEGIN FDCAN1_Init 0 */

 /* USER CODE END FDCAN1_Init 0 */

 /* USER CODE BEGIN FDCAN1_Init 1 */

 /* USER CODE END FDCAN1_Init 1 */
 hfdcan1.Instance = FDCAN1;
 hfdcan1.Init.FrameFormat = FDCAN_FRAME_FD_BRS;
 hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
 hfdcan1.Init.AutoRetransmission = ENABLE;
 hfdcan1.Init.TransmitPause = DISABLE;
 hfdcan1.Init.ProtocolException = DISABLE;
 hfdcan1.Init.NominalPrescaler = 4;
 hfdcan1.Init.NominalSyncJumpWidth = 4;
 hfdcan1.Init.NominalTimeSeg1 = 15;
 hfdcan1.Init.NominalTimeSeg2 = 4;
 hfdcan1.Init.DataPrescaler = 2;
 hfdcan1.Init.DataSyncJumpWidth = 8;
 hfdcan1.Init.DataTimeSeg1 = 31;
 hfdcan1.Init.DataTimeSeg2 = 5;
 hfdcan1.Init.MessageRAMOffset = 0;
 hfdcan1.Init.StdFiltersNbr = 0;
 hfdcan1.Init.ExtFiltersNbr = 64;
 hfdcan1.Init.RxFifo0ElmtsNbr = 32;
 hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64;
 hfdcan1.Init.RxFifo1ElmtsNbr = 32;
 hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64;
 hfdcan1.Init.RxBuffersNbr = 0;
 hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_64;
 hfdcan1.Init.TxEventsNbr = 0;
 hfdcan1.Init.TxBuffersNbr = 0;
 hfdcan1.Init.TxFifoQueueElmtsNbr = 32;
 hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
 hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_64;
 if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) {
 Error_Handler();
 }
 /* USER CODE BEGIN FDCAN1_Init 2 */

 /* USER CODE END FDCAN1_Init 2 */
}
/* FDCAN2 init function */
void MX_FDCAN2_Init(void) {
 /* USER CODE BEGIN FDCAN2_Init 0 */

 /* USER CODE END FDCAN2_Init 0 */

 /* USER CODE BEGIN FDCAN2_Init 1 */

 /* USER CODE END FDCAN2_Init 1 */
 hfdcan2.Instance = FDCAN2;
 hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
 hfdcan2.Init.Mode = FDCAN_MODE_NORMAL;
 hfdcan2.Init.AutoRetransmission = ENABLE;
 hfdcan2.Init.TransmitPause = DISABLE;
 hfdcan2.Init.ProtocolException = DISABLE;
 hfdcan2.Init.NominalPrescaler = 5;
 hfdcan2.Init.NominalSyncJumpWidth = 2;
 hfdcan2.Init.NominalTimeSeg1 = 13;
 hfdcan2.Init.NominalTimeSeg2 = 2;
 hfdcan2.Init.DataPrescaler = 5;
 hfdcan2.Init.DataSyncJumpWidth = 4;
 hfdcan2.Init.DataTimeSeg1 = 13;
 hfdcan2.Init.DataTimeSeg2 = 4;
 hfdcan2.Init.MessageRAMOffset = 0;
 hfdcan2.Init.StdFiltersNbr = 32;
 hfdcan2.Init.ExtFiltersNbr = 0;
 hfdcan2.Init.RxFifo0ElmtsNbr = 64;
 hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
 hfdcan2.Init.RxFifo1ElmtsNbr = 64;
 hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
 hfdcan2.Init.RxBuffersNbr = 0;
 hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
 hfdcan2.Init.TxEventsNbr = 0;
 hfdcan2.Init.TxBuffersNbr = 0;
 hfdcan2.Init.TxFifoQueueElmtsNbr = 32;
 hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
 hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
 if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) {
 Error_Handler();
 }
 /* USER CODE BEGIN FDCAN2_Init 2 */

 /* USER CODE END FDCAN2_Init 2 */
}

 

[Mahmoud Ben Romdhane]

Hello @ricky-fleet ,

 

The Message Ram Offset is well implemented on FDCAN1.

 

Thanks.

Mahmoud

 

 

[ricky-fleet]

Thank you for clarification @Mahmoud Ben Romdhane, I manually updated my H7 software package in CubeMX and can see the setting now! (Not sure exactly when it was added, but it definitely appears in CubeMX version 6.16.0 with STM32H7 version 1.12.1).