STM32H753 ADC Clock Prescaler can not be set to 1

[HCui]

I chose STM32H753IIT6 MCU for my project.

I had set the clock prescaler of ADC to "Asynchronous clock mode divided by 1", and the ADC clock source is PLL2P, 36MHz.

The code was generated successfully. However, I found that the sampling rate is half of the theoretical value.

I migrate the same code to one STM32H743 developing board, all settings are the same with the STM32H753 project. Everything works properly.

Then I set the frequency of PLL2P to 72MHz, CubeMX set the prscaler to "Asynchronous clock mode divided by 2" automatically. I changed it back to "ADC_CLOCK_ASYNC_DIV1" manually in my code. ADC still works fine and the sampling rate is correct then.

Is this a bug?

My CubeMX version: 6.4

HAL version: 1.9.1

[KiptonM]

Probably. the MX program seems to have a lot of bugs of that type. They are working on it. I ran into it twice this week.

My recommendation is when you run into this, fix it where they give you a chance to add your own code at the end of the ADC initialization in main and make a comment that it is a fix for the MX program bug, so you will remember it in 6 months when they fix the MX program.

[HCui]

Thanks for your recommendation.

[Amel NASRI]

Hi @HCui​ ,

This looks like a know issue reported in STM32H755ZI-Q CubeMX Does not generate ADC clocks.

This is recognized for STM32CubeMX 6.5, but here you said that you are using STM32CubeMX 6.4.

-Amel

[HCui]

Thanks for your reply.

Yes, the confugration was done in CubeMX 6.4. The ADC does not work in CubeMX 6.5, so I downgraded to 6.4.

In my case, The ADC clock was generated but the frequency is the half of it shoud be.

I did an experiment to verify my suspicions. I configued the ADC source clock to 72MHz in CubeMX, which is the twice of the max frequency, but modifed the clock prescaler to "DIV1" in my code. But the ADC still wroks properly and I got the sampling rate I wanted.