Using STM32CubeMX 6.3.0 with a dual core STM32H755 micro there is no obvious way to set GPIO context so the same CubeMX pin is defined in both cores

[GHolc.1]

Using STM32CubeMX 6.3.0 with a dual core STM32H755 micro I have a dip switch I wish to be able to read from both cores. Some peripherals (like TIM1 for example) have check boxes for runtime contexts that let you check M7 and M4 to access the peripheral from both cores and define which core contains the initialization. For the GPIO the CubeMX 6.3.0 GUI has drop box selectors instead of check boxes that force choice of M7 or M4 or free, it doesn't look like there is a way to have CubeMX place the pin name definitions into the generated code for both cores. Is there a clean work around besides just going around CubeMX and programming it manually?

[Khouloud OTHMAN]

Hi @Community member​ ,

First let me thank you for raising this point.

Currently what CubeMX deliver is the generation of pin initialization when a specific context is selected for that pin from the drop down list:

With this being said, I'll raise your request internally to be reviewed and to see how we can address a modification.

I'll keep you posted with updates.

Thanks for your contribution.

Khouloud.

[YBast]

Hello, I have the same issue. Has there been a modification to CubeMX, or is there a plan to make a change?
Thanks,
Yves.