Can someone with internal knowledge confirm that the LIS3DSH in I2C mode never drives the SCL line low and that a standard "single master push-pull SCL" can be used in combination with the bidirectional SDA line.

[LeiNie]

The LIS3DSH datasheet contains the following text (not very clear):

"If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW, to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line"

I guess it should have been "the clock line" - anyway I have implemented the I2C bus as a single master SCL-push-pull / SDA-bidirectional - and it works flawlessly at 100KHz - but before releasing this for final PCB design I would like a confirmation of my SCL-push-pull approach.

- thanks in advance.

Best regards

Leif