FIFO timestamp (LSM6DSM)

[LHeit.1]

Hi,

i was trying to set up the pedometer and timestamp functionality for the FIFO.

I was fallowing the instructions on page 102 (chapter 9.1) of the documentation for the setup (high timestamp resolution).

It is working on a FIFO ODR of 104Hz. But if i go higher with the ODR, I do get timestamp duplicates in the FIFO buffer.

So the first 3 readings are at 2 for the timestamp.

Are there any limitations on the use of the fifo timestamp?

The results seem to be valid for 104Hz. With a FIFO ODR of 208Hz, e. g. I should get a timestamp counter difference of round about 192LSB (=192*25μs=4.8ms).

Am I missing something?

Thank you very much

[Eleon BORLINI]

Hi @LHeit.1​ ,

if you are referring to the timestamp as embedded function, I suggest you to have a look to this C example on Github --> lsm6dsm_timestamp.c

Otherwise, if you are interested in the FIFO timestamp, you can check the Step counter and timestamp data in FIFO paragraph of the AN4987 application note. I report it here for simplicity:

Follow these steps to store timestamp and pedometer data in the FIFO using either the internal trigger (accelerometer/gyroscope data ready) or the ‘step detected’ method:
 
1. Turn on the accelerometer;
2. Enable the timestamp and pedometer (see Section 6.1 Pedometer functions: step detector and step counter and Section 6.5 Timestamp);
3. Choose the decimation factor for the 4th FIFO data set through the DEC_DS4_FIFO[2:0] bits of the FIFO_CTRL4 register;
4. Set to 1 the TIMER_****_FIFO_EN bit in the FIFO_CTRL2 register;
5. Configure the bit TIMER_****_FIFO_DRDY in the FIFO_CTRL2 register in order to choose the method of storing data in the FIFO (internal trigger or every step detected);
6. If an internal trigger is used, choose the FIFO ODR through the ODR_FIFO_[3:0] bits of the FIFO_CTRL5 register. If ‘step detected’ trigger is used, no need to set the ODR_FIFO_[3:0] bits;
7. Configure the FIFO operating mode through the FIFO_MODE_[2:0] field of the FIFO_CTRL5 register

-Eleon