Hi @FViga.1 ,
I understand your point.
I think that here the issue could be more related to false negatives than to false positives. Let me explain a little better: if the Vdd drops below 1.62V, the device switches off and the interrupt won't be raised even in the case you should raise it (wake-up event); if instead the Vdd, that is let's say 1.8V increases up to 3V, the event will be anyway detected and notified to the application processor. The accuracy of the event detection should not be impacted, since the internal voltage reference of the analog block of the sensor is always regulated at the same level, and the digital levels are instantaneously linked to the Vdd level.
>> Will it be higher when supplied with 3.6V?
The IIS2DLPC will consume a little more at Vdd = 3.6V than at 1.8V, but the main component of this consumption depends on the ODR and the I2C/SPI communication time. In the same ODR condition, the current consumption increase as depicted in the picture below (LPM1 ODR 50Hz with Low noise Disabled):
I cannot disclose the fully device characterization, but this is a general trend that well fits also other operating modes / ODR cases.
-Eleon