ISM330DHCX - SPI driven by FPGA - some questions
Hi,
I want to drive an ISM330DHCX by an FPGA using SPI. Due to the fast operation and the exact timing I can realise this way, a few questions occured.
- Data sheet fig. 6 details the SPI timing. There is no value given for minimum time for CS=HIGH, i.e. the minimum time between two consecutive bus cycles. Am I right with e.g. 50 ns minimum CS=HIGH?
- Which time is necessary to internally settle written register values, i.e. which time I have to wait before i) I can read written values back and ii) written values are internally valid (e.g. ODR or full-scale selection)?
- A more general question: What is the meaning of CTRL9_XL bit 1 "DEVICE_CONF"? In the data sheet is written "It is recommended to always set this bit to 1 during device configuration.", but in STM's demo applications (STMems_Standard_C_drivers/ism330dhcx_STdC/example/) this register is not used at all.
