LIS25BA TDM interface restrictions

[DRodi.1]

Hi

I am trying to add LIS25BA to be used under TDM along with another device. I have found that LIS25BA datasheet and LIS25BA application note are not match accurately. Could you please help me understand following moments:

Datasheet (chapter 4.2):

The function of the WCLK is simply to identify the beginning of a frame. In particular the frame start at the rising edge of WCLK, and the WCLK widths supported are:
- 50% duty cycle
- One slot width (16 BCLK)
- One BCLK width

app note (chapter 3.2):

The function of the WCLK signal is simply to identify the beginning of a frame; in particular the frame starts at the
rising edge of the WCLK signal. The supported WCLK widths are:
• 16-slot width (1024 BCLK periods, 50% duty cycle);
• One-slot width (16 BCLK periods);
• One BCLK period.

Question 1: is LIS25BA supports only 16-slot TDM? (not very clear from datasheet)

Question 2: why 16-slot width TDM has 1024 BCLK perios? It should be ([bits_per_slot] * [slots_per_tdm] = 16 * 16 = 256, not 1024 BCLK). Am I wrong?

App note chapter 4.1: Startup sequence 
1. Write CTRL_REG = 00h // Normal mode
2. Provide MCLK, BCLK and WCLK to TDM interface
3. Write TDM_CTRL_REG = 0xxx0000b // TDM enable and configuration selection
4. Wait 4.5 ms // Wait the duration of the turn-on time
5. Start gathering acceleration data from TDM interface

Question 3: is it necessary to set TDM_CTRL_REG exactly 0xxx0000b during startup sequence? 16kHz it should (my case) it should be 0xxx0010b.

[Eleon BORLINI]

Hi @DRodi.1​ , try to answer to your question here below:

Question 1: is LIS25BA supports only 16-slot TDM? (not very clear from datasheet)

The TDM structure of the LIS25BA is 8 slot of 16 bits for each slot. You can decide where to map the 3 axis value, either on slot N. 0,1,2 or on N. 4,5,6. This is described in the datasheet p.17. You can also decide the "speed" of the data reading, following the formula WCLK = BCLK/8*16

Question 2: why 16-slot width TDM has 1024 BCLK perios? It should be ([bits_per_slot] * [slots_per_tdm] = 16 * 16 = 256, not 1024 BCLK). Am I wrong?

1.024 MHz is the minimum BLCK value. This corresponds to WCLK of 1.024 MHz/128 = 8kHz

Question 3: is it necessary to set TDM_CTRL_REG exactly 0xxx0000b during startup sequence? 16kHz it should (my case) it should be 0xxx0010b.

No, it is not necessary. You can start with TDM_CTRL_REG = 0xxx0010b value.

As a general consideration, please refer to the datasheet info if you are finding any discrepancies.

Regards

[JPark.25]

Thank you for your input. I also have same question. If get the answer, it is helpful to me. Thanks again.