LIS2DE12 coherency in bypass mode
Hi,
I am using an LIS2DE12 in I2c mode. During setup, my code:
- wrote 0 to CTRL_REG4 (BDU=0, FS=00, ST=00, and SIM=0)
- wrote 0 to CTRL_REG2 (no high-pass filtering)
- wrote 0 to CTRL_REG5 (disable FIFO)
- wrote 0 to FIFO_CTRL_REG (selects Bypass mode)
- wrote 0b00111111 to CTRL_REG1 (sets ODR to 25Hz (40ms), LPen=1, X=1, Y=1, Z=1 which enables all 3 axes).
Then, approximately once every 100ms, my code does the following:
- It reads STATUS_REG and confirms that the 3 least significant bits are all 1.
- With one I2c transaction, it reads 5 bytes starting with register 0x29 (with the 0x80 bit set). This gives me the value from OUT_X_H in the first byte, OUT_Y_H in the third byte, and the value from OUT_Z_H in the fifth byte.
Will the values I get from OUT_X_H, OUT_Y_H, and OUT_Z_H always be coherent, i.e. from the same measurement?
OR is it possible that the chip could update some of these registers with a new measurement at the same time that my I2c transaction is reading them, such that one or two of the numbers I get are from one measurement (A) and the other number(s) I get are from a different measurement (B)?
If the answer is that they could be from different measurements, what strategy & algorithm should I use to guarantee that I always obtain a coherent vector from the latest measurement?
Thanks in advance.
