LIS2DE12 interrupt configuration

[timothy0508]

I am currently working on the LIS2DE12 accelerometer. I've been reading the datasheet and I was a little confused with the interrupt configuration. The datasheet says the device provides 2 interupt pins (INT1 and INT2). 

1. My understanding is that you can use either the INT1 pin or the INT2 pin. Is this correct?

What's the reccommended practice?

2. In the CTRL_REG6 register, there are two bits I2_IA1 and I2_IA2 for configuring interrupts. Specifically what does "interrupt 1 function", interrupt 2 function" and "activity interrupt" mean?

Thanks

[Eleon BORLINI]

hi Timothy

1. Yes, the two interrupts can be independently configured, using INTx_CFG, ... registers. In particular, INT1_SRC is the Interrupt 1 source register while INT1_SRC is the Interrupt 2 source register. 
2. You can route the Interrupt 1 and the Interrupt 2 generated respectively from INT1_SRC and INT2_SRC on the INT1 physical pad or the INT2 physical pad by configuring I2_IA1 bit or I2_IA2 bit, as per your needs (same for I1_IA1 and I1_IA1 bits of reg CTRL_REG3)

Interrupt 1 and Interrupt 2 are the interrupt flags (bits in the registers), while INT1 and INT2 are the physical pads, to which the interrupt flags can be independently connected.

Regards

[timothy0508]

Thanks so much for your response. That helps a lot. Follow up questions:

1. What happens then if both bits I2_IA1 and I2_IA2 are set?
2. In CTRL_REG5, there is the BOOT bit, which "reboots memory content". Does "reboot" in this context mean reset all registers to their default values, and when does the reset happen (when the device powers up or when the bit is set)?
3. For the INT1_DURATION, could you please explain "1 LSb = 1/ODR "? (an example would very much be appreciated).

Thanks again.

[Eleon BORLINI]

hi timothy, you're welcome

1. both interrupt 1 and 2 have the same priority, so if they are routed on the same INT2, the first . It is not a suggested configuration however...
2. Consider the DS caption: Registers that are loaded at boot contain the factory calibration values. Their content is automatically restored when the device is powered up (same if CTRL_REG5 bit BOOT = 1). The boot procedure is complete within 5 milliseconds after device power-up (same if CTRL_REG5 bit BOOT = 1).
3. 1/ODR is the smallest duration for an interrupt event to be recognized. For examples, you are running at 100Hz ODR: in this case, you can detect an event that lasts at leas 10ms if the INT1_DURATION reg value is 01h. If you write the value 02h in the same register, the minimum detectable event will be of 20ms duration and so on...

Regards

[Eleon BORLINI]

The "activity interrupt" is the interrupt generated by the Sleep-to-wake and/or Return-to-sleep events, adjustable acting on ACT_THS (3Eh) and ACT_DUR (3Fh) registers

[PHaav]

Hi,

I am struggling with very similar issues that timothy0508 was asking about.

The answers were quite helpful, but I would still like to understand better.

1) What does the BOOT bit in control register 5 do, and when does it do it? Should it reset all registers immediately when the bit is set by writing to the register? Does it also then reset itself automatically, or should I reset it some time after setting it? In my own testing it does not seem to reset ever...

2) You wrote: "1/ODR is the smallest duration for an interrupt event to be recognized. For example, you are running at 100Hz ODR: in this case, you can detect an event that lasts at least 10ms if the INT1_DURATION reg value is 01h."

But the default value for the duration register is 0. I understand that so that the smallest duration is then anything above zero, and less than 1/ODR? Or are you saying that the value 0 in the DURATION register is the same as value 1 and interrupt events shorter than 1 are never recognized?

Thanks for any further help you can provide!

Petri