LIS2DH taking 100-120uA in idle state after a power cycle

[PK.1]

I am using LIS2DH in I2C mode. After power cycle, the IC consumes almost 100-120 uA. Upon removing the IC current drops to 30 uA so clearly it is the IC that is consuming the power.

After startup, I am resetting the IC, blocking the data (0x80 in REG 0x2E) and rebooting memory content (0x80 in REG 0x2F). But still there isnt any change.

I noticed, every time fifo is getting filled up to 32 values, though it has not been configured to collect data and FIFO is disabled

Please advise/

[Eleon BORLINI]

Hi @PK.1​ ,

Please note that once the LIS2DH device is powered up, it automatically downloads the calibration coefficients from the embedded flash to the internal registers. When the boot procedure is completed, i.e. after approximately 5 milliseconds, the device automatically enters power-down mode. So if there is some over-current consumption after this procedure and before the first SPI of I2C communication with the sensor, there could be some issue in the hardware connection / schematic. Can you please share it or check if it is coherent for example with the STEVAL-MKI135V1 one? Vdd and VddIO can be tied together.

Please note also that if you write the value 0x80 in REG 0x2E you are configuring the FIFO Stream mode, see LIS2DH datasheet, p.21, and you have to consider it in the calculation of the overall power consumption of the device... Are you configuring the right part number?

-Eleon

[PK.1]

Hi Eleon,

Thank you for the kind response.

Sorry the register configuration was wrong on my part - I double checked.

However, without configuring - on a power cycle - it still consumes 150 uA.

This is my schematic and I made connections just as in reference design.

We got boards made from 2 manufacturers and all boards test like this. Please advise.

Thanks,

Prathyusha

[PK.1]

Eleon -

After powerup, I set BDU and BOOT by writing 0x80 to 0x23 and 0x24 registers as per the LIS2DH datasheet. The power dropped a few uA but no significant change.

Please advise.

Thank you.

[Eleon BORLINI]

Hi @PK.1​ ,

the hw connections looks ok... can you try to separate Vdd and VddIO and try to power them separately?

-Eleon

[PK.1]

Hi Eleon -

I am unable to separate Vdd and VddIO on my board currently as the board doesn't have that provision.

Can you please let me know more about the internal pad types of SDA and SCL lines on the LIS2DH? (pulled up or opendrain or tri-state)

Would the pad type incompatibility cause high current draw?

Please advise.

Thanks,

Prathyusha

[Eleon BORLINI]

Hi @PK.1​ ,

I checked and the SDA and SCL lines on the LIS2DH ASIC should be internally connected to positive supply voltage via (weak) pull-up resistors. So, if you force them to GND through application processor, you could experience an over-current consumption (150uA is somehow high and the pull-up path consumption should in case be dominated by your 4.7kOhm resistors, but can try to leave these pin floating at AP side).

-Eleon

[PK.1]

Hi @Eleon BORLINI​ 

Can you also check how is the SA0 line internally in the LIS2DH?

In my schematic, it is connected to ground externally, so want to know if that can be the cause of high 150 uA power consumption.

Please let me know.

[Eleon BORLINI]

Hi @PK.1​ ,

SDO / SA0 pad (PIN#3) in effectively an Input/output pad with disconnectable active pull-up. The default pull-up value is about 50kOhm for a Vdd = 1.8V and decreases with the Vdd increasing. I can say you that to disconnect pull-up you should write ‘1’ in bit MSB of the reserved 1Eh register, but since this information is not in the datasheet, you should pay attention to these actions. You can try and see if the Idd decreases, but please take care of masking the other 1Eh-register bits.

-Eleon

[PK.1]

Hi Eleon -

Thanks for this important information.

Just to confirm, the most significant 'bit' right? so write 1xxxxxxx to 0x1E register, correct?

Please confirm.

Thanks!

Prathyusha