LIS2DH12 FIFO after interrupt.

[TGeld.1]

Dear community,

i have one more problem with my lis2dh12 project.

So my sensor run in STREAM-TO-FIFO mode.

After init. i can interrupt my sensor und get the right data.

After some time my uC go into sleepMode (deinit i2c bus).

When i trigger my lis2dh12 again, my uC start, i init the i2c bus and read out the FIFO.

But there are no values from my shock. But if i trigger my sensor again before my device go again into sleep there are right data. Did the sensor reset his FIFO after reinit i2c?

I check my register after and before sleep and this seems look ok.

EDIT:

After a few more tests, it looks like the FIFO isn't "freezing". If I read directly after the interrupt, all good. If I insert a delay of a few seconds before that, there is no more data from the shock in the FIFO.

Here is a dump from my reg.

[ACC] 00 : 10	CTRL_REG0 
[ACC] 01 : 00	TEMP_CFG_REG 
[ACC] 02 : 5F	CTRL_REG1 rw
[ACC] 03 : 00	CTRL_REG2 rw 
[ACC] 04 : 00	CTRL_REG3 rw 
[ACC] 05 : 30	CTRL_REG4 rw 
[ACC] 06 : 48	CTRL_REG5 rw 
[ACC] 07 : 40	CTRL_REG6 rw 
[ACC] 08 : 00	REFERENCE rw 
[ACC] 09 : FF	STATUS_REG r 
[ACC] 0a : 00	OUT_X_L r 
[ACC] 0b : 00	OUT_X_H r 
[ACC] 0c : 00	OUT_Y_L r 
[ACC] 0d : 05	OUT_Y_H r 
[ACC] 0e : 00	OUT_Z_L r 
[ACC] 0f : 00	OUT_Z_H r 
[ACC] 10 : C0	FIFO_CTRL_REG rw 
[ACC] 11 : 9E	FIFO_SRC_REG r 
[ACC] 12 : 2A	INT1_CFG rw 
[ACC] 13 : 15	INT1_SRC r 
[ACC] 14 : 0D	INT1_THS rw 
[ACC] 15 : 00	INT1_DURATION rw
[ACC] 16 : 00	INT2_CFG rw 
[ACC] 17 : 00	INT2_SRC r 
[ACC] 18 : 00	INT2_THS rw 
[ACC] 19 : 00	INT2_DURATION rw
[ACC] 1a : 00	CLICK_CFG rw 
[ACC] 1b : 00	CLICK_SRC r
[ACC] 1c : 00	CLICK_THS rw 
[ACC] 1d : 00	TIME_LIMIT rw 
[ACC] 1e : 00	TIME_LATENCY rw 
[ACC] 1f : 00	TIME_WINDOW rw 
[ACC] 20 : 00	ACT_THS rw

[Eleon BORLINI]

Hi @TGeld.1​ ,

Regarding this point:

>> After a few more tests, it looks like the FIFO isn't "freezing". If I read directly after the interrupt, all good. If I insert a delay of a few seconds before that, there is no more data from the shock in the FIFO.

Please consider this passage in the Application note AN5005:

In Stream mode the FIFO buffer continues filling, when the buffer is full, the OVRN_FIFO bit is set high and the next samples overwrite the oldest. When a trigger occurs, two different cases can be observed:

1. If the FIFO buffer is already full (OVRN_FIFO = “1�?), it stops collecting data at the first sample after the trigger. FIFO content is composed of #30 samples collected before the trigger event, the sample that has generated the interrupt event and one sample after the trigger.

2. If FIFO isn’t yet full (initial transient), it continues filling until it is full (OVRN_FIFO = “1�?) and then, if the trigger is still present, it stops collecting data. 

You should be sure that the interrupt is still present at the end of the FIFO filling. You might try to latch the interrupt. Check also the C Github example --> lis2dh12_read_fifo.c

-Eleon