LIS2DTW12 Threshold setting

[RStra]

Hello,

I read the application note related to the LIS2DW12 (AN5038) and the point 6.5 confused me :

 

On the table is recommended to set FTH_THS at 8 if the ODR is 200 Hz and I2C is running at 100KHz.

A sample of 3 acceleration (6 bytes) is read in 830 uS and every 5mS (1/ODR) there is a new sample.

With 8 as FTH_THS read the 8 samples on the buffer takes 6.64mS, so in my understanding at the end of the reading the FIFO contains only a new samples.

My questions are:

1) Why the FTH_THS is set to 8 ?

2) If the reading of a samples (3 acceleration of 2 bytes) takes in the worst case 830 uS, and a new samples is created every 5mS (1/ODR) why I can not set the FTH_THS at 32 ? In my understanding every times I read from the FIFO the oldest sample is discarded so there is a new free row on the FIFO.

Regards,

Riccardo

[TBomb.1]

Hello Riccardo, you wrote:

-- With 8 as FTH_THS read the 8 samples on the buffer takes 6.64mS, so in my understanding at the end of the reading the FIFO contains only a new samples.

But 8 samples takes 29 clocks + 6 (2 bytes per 3 axes) * 9 (clock cycles) * 8 (threshold) = 461, meaning 4.61ms for a speed of 100kHz.

The ODR is 200Hz, so correctly 1/ODR is 5ms. This is the time during which you must read the FIFO, since otherwise the new sample (after 1/ODR) will be lost (FIFO stops collecting data during it is read).

Or at least I interpreted it that way.

\Tom