LIS2DW12 generate extra interrupt within "quiet" period for single tap event

[MHo.0]

Hi,

I'm working on enabling single tap detection on LIS2DW12. I found it generates multiple interrupts for one single tap. After I check the signal on oscilloscope in one of the single tap event, the 2 interrupts are seen within 20 ms which I should have 30 ms quiet period set. Can you please check how to configure the sensor properly to avoid this? Thank you.

Min-Ching

Register dump:

093085 0x0D (OUT_TEMP_L): 0xD0

093085 0x0E (OUT_TEMP_H): 0xFF

093087 0x0F (WHO_AM_I): 0x44

093088 0x20 (CTRL1): 0x74

093089 0x21 (CTRL2): 0x04

093089 0x22 (CTRL3): 0x18

093090 0x23 (CTRL4): 0x40

093091 0x24 (CTRL5): 0x00

093091 0x25 (CTRL6): 0x04

093092 0x26 (TEMP_OUT): 0xFF

093093 0x27 (STATUS): 0x21

093093 0x28 (OUT_X_L): 0x10

093094 0x29 (OUT_X_H): 0x0D

093095 0x2A (OUT_Y_L): 0x10

093095 0x2B (OUT_Y_H): 0x04

093096 0x2C (OUT_Z_L): 0xB0

093097 0x2D (OUT_Z_H): 0x3D

093098 0x2E (FIFO_CTRL): 0x3E

093098 0x2F (FIFO_SAMPLES): 0x00

093099 0x30 (TAP_THS_X): 0x8F

093100 0x31 (TAP_THS_Y): 0x0F

093101 0x32 (TAP_THS_Z): 0xEF

093101 0x33 (INT_DUR): 0x3F

093102 0x34 (WAKE_UP_THS): 0xCA

093103 0x35 (WAKE_UP_DUR): 0x42

093104 0x36 (FREEFALL): 0x00

093105 0x37 (STATUS_DUP): 0x61

093106 0x38 (WAKE_UP_SRC): 0x10

093106 0x39 (TAP_SRC): 0x00

093107 0x3A (SIXD_SRC): 0x02

093108 0x3B (INT_SRC): 0x00

093109 0x3C (X_OFS): 0x00

093109 0x3D (Y_OFS): 0x00

093110 0x3E (Z_OFS): 0x00

093111 0x3F (CTRL7): 0x20

Scope view:

[Eleon BORLINI]

Hi Min-Ching,

Your settings seems ok, except from WAKE_UP_THS value in line:

>> 093102 0x34 (WAKE_UP_THS): 0xCA

According to the procedure described in the app note AN5038 (par 5.6.4, p.29), you should set 00h in WAKE_UP_THS register, or at least write “0�? in bit<7> (par. 8.24 of the datasheet document (DS), p.47), at least if you are working latched in SINGLE_TAP mode. In fact:

If latch mode is enabled and the interrupt signal is driven to the interrupt pins, the value assigned to SINGLE_DOUBLE_TAP also affects the behavior of the interrupt signal: when it is set to 0, latch mode is applied to the single-tap interrupt signal; when it is set to 1, latch mode is applied to the double-tap interrupt signal only.

(p.28 of the AN5038)

You could try to disable the bit<7> of reg, or work in pulsed mode (CTRL3 reg settings).

AN reference: https://www.st.com/content/ccc/resource/technical/document/application_note/group0/f1/1b/35/59/dc/e6/45/13/DM00401877/files/DM00401877.pdf/jcr:content/translations/en.DM00401877.pdf

DS reference: https://www.st.com/resource/en/datasheet/lis2dw12.pdf

[MHo.0]

Hi Eleon,

Thank you. I tried to disable LIR on CTRL3. The behavior did change. I saw the interrupt latched to whatever quiet time I set. Does that mean even after I clear the interrupt by reading the register, the interrupt pin will stay until the quiet time finished?

Are you suggesting when in latched mode, the same event could generate 2 interrupts? (e.g. the first pulse in the screen shot is the first time single tap event is recognized. Driver clear the interrupt, and the second interrupt coming in right away because of the quiet time has not finished yet.)

Thank you,

Min-Ching

[Eleon BORLINI]

​If LIR bit = 0, the interrupt is not latched, stays active for the whole "quiet" phase and then resets.

If LIR bit = 1, the interrupt stays latched until you read TAP_SRC or ALL_INT_SRC bits, independently from the "quiet" phase duration.

When latched mode (LIR bit = 1) and SINGLE_DOUBLE_TAP = 1, the latch priority should apply to double-tap interrupt signal only. If your target is to detect a single tap, I think that one solution could be to set the LIR bit = 0 (or SINGLE_DOUBLE_TAP = 0) and manage the interrupt active time by reading the TAP_SRC or ALL_INT_SRC bits, before the "quiet" time elapses. I don't think that there should be a "double" interrupt generation after a single tap (also in case you clear the interrupt), caused by the fact that you refresh the interrupt before the "quiet" condition elapses (BTW, do you clear between the first detected pulse and the other one?)

[MHo.0]

Yes. Whenever the interrupt triggered, i need to read the status registers to get the interrupts as well as clear it.

I don't know how to explain the 'double' interrupt. According to AN5038 section 5.6.2, quote:

"In particular, after the first tap has been recognized, the second tap detection procedure is delayed for an interval defined by the quiet time. This means that after the first tap has been recognized, the second tap detection procedure starts only if the high-pass filtered data exceeds the threshold after the quiet window but before the latency window has expired."

I really don't know how to explain where the second interrupt came from. These 2 interrupts are shorter than the quiet time I set. If it is really came from the other event, I really need your help to identify it.

Thank you,

Min-Ching

[MHo.0]

Another question, not directly related to this topic. If the FIFO is stopped due to fullfill and never re-enable, can LIS2DW12 still detect events?

I'm making the driver to detect double tap as well as shaking. I need to use LIS2DW12 built-in feature to detect double tap to wake up the system. And, use the data inside the FIFO to detect shaking gesture. I found when the system wakeup, it can not see the double tap event sometimes and I need to double tap again. Is there away to have the wake up and double tap event work together?

Thank you,

Min-Ching