LIS3DH in FIFO mode gives garbage output

[BLind.3]

I'm trying to configure a LIS3DH to trigger INT1 after filling FIFO, after which I want to read out everything over I2C and then repeat.

I've gotten it to work (at f=10 Hz, I get INT1 interrupts at the expected ~3 sec interval), but when I read out the data, I get 0x00 values only. When I configure without the FIFO (trigger INT1 on every sample), I get reliable data. But then I added the following:

init:

• CTRL_REG5: flip FIFO_ENABLE bit
• FIFO_CTRL_REG: flip MODE_STREAM bit and set FTH bits to 31
• CTRL_REG3: OVERRUN on INT1 instead of DRDY

on INT1 signal:

• read FIFO_SRC_REG, set N to BITS(0:4) - this is always 31 so it's looking good so far
• loop 32 times: burst read six bytes starting at output reg 0x28 (OUT_X_L)
• Check FIFO_SRC_REG, ensure EMPTY bit is set. It always is.

But when I dump out the data, it's always 0x000000000000. Anyone have any idea what could be going on here?

[Eleon BORLINI]

Hi @BLind.3,

Are you using the Stream-to-FIFO mode mode, described in the AN3308 application note, p.50?

In Stream mode the FIFO buffer continues filling, when the buffer is full, the OVRN_FIFO bit is set high and the next samples overwrite the oldest. When a trigger occurs, two different cases can be observed:

1. If the FIFO buffer is already full (OVRN_FIFO = “1�?), it stops collecting data at the first sample after the trigger. FIFO content is composed of #30 samples collected before the trigger event, the sample that has generated the interrupt event and one sample after the trigger.

2. If FIFO isn’t yet full (initial transient), it continues filling until it is full (OVRN_FIFO = “1�?) and then, if the trigger is still present, it stops collecting data.

You should be in the first case from the above list.

Please have also a look to the C Github examples related to the FIFO multiread:

lis3dh_multi_read_fifo.c

-Eleon