LIS3DH Interrupt always high

[spetcavich]

Posted on May 24, 2017 at 22:07

With the configuration below I'm attempting to receive and interrupt from INT1 when there is acceleration along the Z axis. However INT1 alwyas stays high...Not sure whats going on

//ctrl_reg1

LIS3DH_WriteReg(LIS3DH_CTRL_REG1, 0x24);

//ctrl 2

LIS3DH_WriteReg(LIS3DH_CTRL_REG2, 0x01);

//ctrl_reg3

LIS3DH_WriteReg(LIS3DH_CTRL_REG3, 0x40);

//set Full scale

//ctrl_reg4

LIS3DH_WriteReg(LIS3DH_CTRL_REG4, 0x88);

//ctrl_reg5

LIS3DH_WriteReg(LIS3DH_CTRL_REG5, 0x00);

//int_tsh

LIS3DH_WriteReg(LIS3DH_INT1_THS, 0x7F);

//dur

LIS3DH_WriteReg(LIS3DH_INT1_DURATION, 0x32);

//Zhi interrupt

LIS3DH_WriteReg(LIS3DH_INT1_CFG, 0xA0);

#lis3dh-interrupt #lis3dh

[Miroslav BATEK]

Posted on May 25, 2017 at 12:08

I think the problem is in the interrupt threshold, duration and ODR settings combination.

LIS3DH_WriteReg(LIS3DH_CTRL_REG1, 0x24); ... ODR = 10 Hz

LIS3DH_WriteReg(LIS3DH_INT1_THS, 0x7F); ... Threshold = 2032mg

LIS3DH_WriteReg(LIS3DH_INT1_DURATION, 0x32); ... Duration = 50 * 0.1s = 5s

To trigger the interrupt you would have to expose the sensor to 2g (above 1g of gravity) for 5 seconds, which I think is very difficult.

I don't know what exactly you want to detect, but I would suggest to modify the settings, I mean decrease threshold and duration and/or increase ODR.

[Alexander Maroudis]

Posted on March 05, 2018 at 07:44

I am running into a similar problem.  I have read through some of your posts and configured the registers exactly the same way, but it seems to always be triggering.  This is what I do with the configuration :writeRegister8(ACC_INT1_CFG,0x2A);, I am polling the INT1_SRC register waiting for the movement/Interrupt Active interrupt, but the first time I poll it, the Interrupt Active bit is set and it shows that a low event for X Y and Z havs occured (so the register reads 0x55). I am also looking at the INT1 pin and it is always staying high.  Should those 'low event' bits be set in the INT1_SRC register if they are NOT enabled in the INT1_CFG register?

[Miroslav BATEK]

Posted on March 06, 2018 at 09:06

The bits in INT1_SRC are set even if they are not enable in INT1_CFG, but only enabled condition have impact on the interrupt.

If you provide me your complete configuration I can check it.