LIS3DH Startup Sequence

[Jono]

Hi,

This is my first question to the community so hello! :)

I've recently started working with the LIS3DH accelerometer and I am experiencing some difficulty in interpreting the startup sequence for the device. Using the datasheet and AN3308 the startup sequence is described as the following for a generic configuration:

1. Write Ctrl_Reg1
2. Write Ctrl_Reg2
3. Write Ctrl_Reg3
4. Write Ctrl_Reg4
5. Write Ctrl_Reg5
6. Write Ctrl_Reg6
7. Write REFERENCE
8. Write INTX_THS
9. Write INTX_DUR
10. Write INTX_CFG
11. Write Ctrl_Reg5

For my project I need to first write the configuration to the device in power-down mode and then when prompted set the correct power mode and begin sampling. However the above format seems to begin sampling after the first write to the device once the ODR has been set and axis enabled.

Additionally for signal synchronisation on DRDY the I1_ZYXDA must be set before the ODR.

I would like the device to operate at 50Hz Bypass Mode with 10 bit resolution and the ZYXDA interrupt mapped to INT1 as active high. I would like the device to sit in that configuration in power-down mode until prompted and then I can set the device into normal mode.

Could anyone please advise?

Jono :)

[Miroslav BATEK]

You can do it as you need. Just set the ODR bits to Power-Down mode in the first step. Set the other registers and then write the required ODR settings into CTRL_REG1.

[Jono]

Okay that sounds straight forward enough, thank you! I will give this a try :)

If I were to use the FIFO mode as opposed to BYPASS and put the device into power-down mode, would it be best to switch to BYPASS to clear the FIFO before switching to power-down mode?

[Miroslav BATEK]

It is not mandatory to switch FIFO into Bypass mode, but I think it is good practice. Later when you switch on the sensor you can directly go to selected FIFO mode.

[Jono]

Does that mean that the FIFO is cleared when the device is entered into power-down mode? Additionally, are the registers holding the most recent XYZ values cleared when entered into low-power mode or does that then need following with a read on the MSB registers?

[Miroslav BATEK]

No, the FIFO is not cleared in power-down mode. The latest XYZ value in output registers are also not cleared.