[LSM6DSL] Data loss during reading FIFO data?

[MKang.1]

Hi, I'm testing LSM6DSL FIFO mode. And I have a problem with output data rate.

I don't have the problem with reading the data, but my problem is that average data output is about 96.5 samples per seconds while my ODR setting is 104Hz.

And here is my question:

• While I am reading FIFO data, FIFO data is not updated therefore there can be data loss? If so, can I avoid such situation?
• or if problem comes from other reasons(e.g. internal clock), how can I check what is the source of the problem?

* Current configuration is as follows

• FIFO_MODE_[2:0] is 0b110 'continuous mode and if the FIFO is full the new sample overwrites the older one' (FIFO_CTRL5: 0x26, FIFO ODR is 104Hz)
• BDU enabled (CTRL3_C: 0x44)
• FIFO depth is limited to threshold level (FIFO_CTRL4: 0x80)
• 104Hz ODR Acc+Gyro with 26*6 FIFO threshold level( CTRL1_XL: 0x44, CTRL2_G: 0x4C, FIFO_CTRL1: 0x9C)
• SPI communication

[MKang.1]

I changed the way to read FIFO, and it is much better.

Before I read 12 bytes from FIFO (ACC+GYRO 1 sample) and transfrom each sample, and then read next 12bytes from FIFO register... and so on.

Now I get 101~102 samples per seconds. Still I'm wodering if what can be done to enhance effective ODR (including FIFO reading).

[Eleon BORLINI]

Hi @MKang.1​ , you should select FIFO mode as (ds p.57):

FIFO_MODE_[2:0] --> 001 FIFO mode. Stops collecting data when FIFO is full (or reach the defined threshold).

and read FIFO only once after it is full up to your threshold, setting the SPI clock >1MHz suggested.

Btw, a full-flag interrupt can be enabled, INT1_CTRL (0Dh)(INT_ FULL_FLAG) = '1', in order to indicate FIFO saturation and eventually read its content all at once. You can trigger your SPI data readings on this interrupt. Regards

[MKang.1]

Hi Eleon, really appreciate your prompt answer. But if you don't mind, let me bother you with few questions.

- 'FIFO_MODE_[2:0] --> 001 FIFO mode'

: Is this to prevent overwriting older sample in FIFO_MODE_[2:0] --> 110 mode?

- 'SPI clock >1MHz suggested'

: Can I find similar guidance for I2C, too? Because I'm looking for changing from SPI to I2C due to limited circuit configuration.

- 'INT_ FULL_FLAG = '1''

: Currently I enabled 'INT1_FTH' for INT1_CTRL register with STOP_ON_FTH enabled at FIFO_CTRL4 register. It can bring the same result as I understood, right?

[MKang.1]

After I changed from SPI to I2C, I understood the meaning of 'SPI clock >1MHz suggested'.

With 100kHz I2C clock, effective data reading per second decrease almost by 10% where ODR=104Hz ACC+GYRO, FIFO size = 26 6-axis samples (=26*6*2 = 312bytes)

I handled this issue by I2C clock 100kHz->300kHz, and decreasing FIFO size from 26*6(26 6-axis samples) to 8*6(8 6-axis samples). Then decrease rate is about 1 %.

Since it is hard to expect answer for my question 10 days ago, I hope I can get answer for following really specific questions.

1) If ODR is 104Hz, so period is about 10ms, and FIFO reading + clearing FIFO takes 8ms. Under this situation, the first data in next FIFO comes after 2ms(10ms - 8ms) after reading, or after 10ms?

2) Is there FIFO setup which can update FIFO during reading? Though recommendation is BDU = 1.