LSM6DSL interrupt is getting latched after some time.

[pshin.1]

Hi,

I am using LSM6DSL in my project. FIFO is configured for the same and host processor receives the interrupt after FIFO threshold is reached. I have also configured the pulsed mode for the interrupt. After receiving an interrupt, host controller reads the data from FIFO and this cycle continues.

However, I observed that FIFO threshold interrupt pin is getting latched to logic HIGH after some time. Ideally, it should never get latched since the pulsed mode is configured.

I am attaching the graphs in which red colored waveforms represent the data on INT1 pin of LSM6DSL and blue colored waveform represents the data on GPIO which is being toggled in host processor's ISR after the rising edge is detected on INT1 pin.

May I know why INT1 pin is latching to logic high state?

[Eleon BORLINI]

Hi @pshin.1​ ,

it is strange that the FIFO full interrupt latches randomly... did you repeated this test to check if the behavior is repeatable?

Can you also please check in which of the FIFO working mode you are? (See the application note AN5040, p.82)

It looks like you are switching from FIFO into the Continuous-to-FIFO mode...

 

-Eleon

[pshin.1]

Hi Eleon,

I am observing this behavior consistently during my test.

I am configuring the FIFO in bypass mode initially and then switching to FIFO mode only once.

To be more specific about the issue, if there is a delay while reading the FIFO output data registers,

this issue is occurring.

Thanks,

Pranav