LSM6DSL: Interrupts aren't latched when the LIR Bit is set to 1

[Cyrill]

Hello,

Even though I have set the LIR bit to 1, the interrupts aren't latched. In the picture you can clearly see that the interrupt is reset before reading the route register of interrupt 1. The LIR bit is definitely set to 1. I have checked this with lsm6dsl_int_notification_get. Routed to the interrupt 1 is the fifo treshold only. What could be the problem?

Kind regards

Cyrill

[Miroslav BATEK]

LIR doesn't have an impact of FIFO threshold interrupt. FIFO threshold interrupt is cleared as soon as you read one sample from FIFO and the number of samples in FIFO is lower than the threshold.

[Cyrill]

Thank you for your fast reply. There is no way to change this, isn't it?

Many thinks,

Cyrill

[Miroslav BATEK]

Unfortunately not.