120Mhz emissions from SDIO pins

[PCudd]

We are getting massive ammounts of emissions from the D0 SDIO pin with 120mhz and resonant freqs. The pins for SDIO have been set to AF but nothing else has been setup register wise yet, the circuit was taken from the appnotes with the 3v3 pullups on D0,1,2,3,CMD

APB2 periph is 60mz

APB2 timer 120mhz

[Javier1]

@PCudd​ 

How about you show us your PCB layout or something.

What does AF mean?

How do you know the noise is comming from the SDIO pins?

[PCudd]

Hi Javier, Thank you for the reply.

Alternate Function for the SDIO pins in the GPIO MODE Registers

top and bottom copper

Ground plane in between 

We probed the pins with an analyzer this is directly probing the D0 pin

This is probing both pins next to D0

[Javier1]

wow,

no idea of where the SDIO pins are in your pcb, but it looks like a noise playground for high frequencies.

Is this a new problem? Or have you been using SDIO withour problems untill now?

[Ozone]

Besides of possible configuration and wiring issues with the SDIO pin, the PCB track seems to function as a perfect antenna for said frequencies, i.e. length and impedance matching seem to favour such transmissions.

[PCudd]

Do you suggest keeping the track lengths to a minimum?

[Ozone]

I am no PCB designer, just had to collaborate with them occasionally.

Normal SPI/SDIO lines contain at least terminating resistors, check e.g. available schematics.

Making the track longer or shorter will change the resonance frequency, and thus "shift" the problem to another point.

You might need to collaborate with the SW designer and the project management in this regard.

There are PCB design tool available that include a RF analysis (before even prototyping), though they tend to be not cheap ...