access to external ram

[jm]

Posted on February 25, 2004 at 12:57

access to external ram

[jm]

Posted on February 25, 2004 at 10:06

Hi,

I work on ST10F168 and i use 2 64K*8bits SRam chip like one 64K*16bits Sram chip.

My problem is that i don't understand to use BHE and A0 signal.

I find 2 configurations :

1) WR signal on WR of first chip

BHE signal on WR of second chip

CS1 on CS of 2 chip

Adress A1->A16 on A0->A15 of 2 chip

First chip data : low (POL)

second chip data : high (POH)

2) WR signal on WR of 2 chip

BHE signal on CS on first chip

A0 signal on CS of second chip

adress P1H on A8->A15 of first chip

adress P1L on A0->A7 of second chip

First chip data : low (POL)

Second chip data : high (POH)

So, i don't see the difference between the 2 configurations !

If someone can explain to me the differences or advantages.........

Thanks

regards,

Jim

[charles239955_st]

Posted on February 25, 2004 at 12:35

Hello.

In the St10 BUSCON register you have a lot of configurations possible. And it is also related to the SYSCON regsiter bit 7: WRCFG. With this bit you select the way the pins /WR and /BHE are working.

1/ If WRCFG = 0, you have the pin /WR = write and /BHE = byte high enable

This corresponds to your configuration 2 below.

The /WR signal is always connected to the 2 SRAMs. When you need to perform an 8 bit access, ''chip select'' will enable the correct SRAM.

For the high byte, the chip select signal is /BHE, for the low part it is A0 address line.

2/ If WRCFG = 1, the pin /WR is the signal /WRL = write low

and the pin /BHE is /WRH = write high.

This corresponds to your configuration 1. The CS always enables both SRAMs but for 8 bit write access only 1 SRAM get an active write signal.

The selection between the 2 modes depends on the SRAM you have because the timings are not the same in the 2 cases: check the need of your SRAM with regard to CS active before/after Write signal. Have a look to the datasheet AC timings part where you have chronograms for the signal.

Also your configuration 2 can not be used if you have several devices on the external bus because the SRAMs may answer for any read/write action as the chip select in not based on a window range.

I hope I helped you.

Regards,

Kenshin

[jm]

Posted on February 25, 2004 at 12:57

thanks for your precision !