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Visitor II
January 18, 2006
Question

ADC varying results

  • January 18, 2006
  • 5 replies
  • 1096 views
Posted on January 18, 2006 at 05:24

ADC varying results

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    5 replies

    tj2Author
    Visitor II
    January 17, 2006
    Posted on January 17, 2006 at 09:51

    Hi

    While testing the ADC on our target board, I see that the converted result very often varies a lot or jump to a completely way off value. How can this be?

    The circuit is bandwith limited to 250Hz and the prescaler is configured to a samplerate of 500Hz.

    tj2Author
    Visitor II
    January 17, 2006
    Posted on January 17, 2006 at 09:59

    [ This message was edited by: logic_io-TJ on 17-01-2006 14:32 ]

    Visitor II
    January 18, 2006
    Posted on January 18, 2006 at 03:59

    Hi logic

    As the STR71x reference manual the ADC out put result is such the attached picture.

    The converted value stored in ADC_DATA[n] is a signed two’s complent value and proportional to the difference (VIN-VCM).

    Can you tell me about the variation rate

    And are you sure of the input source precision?

    With best regards,

    Hich ;)

    ________________

    Attachments :

    ADC_out_put.bmp : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HtAg&d=%2Fa%2F0X0000000aJu%2F7LtrRTVx2kZbV3MkiGtPPCmhVdCpM5MbbwypflxcdPQ&asPdf=false
    tj2Author
    Visitor II
    January 18, 2006
    Posted on January 18, 2006 at 04:27

    Hi Hich

    At one input the source is a DC power supply, trimmed to output exactly 2,500V. The other input is connected to ground through a 10k resistor (to calculate the gain and offset). Both inputs are of course bandwidth limited to 250Hz.

    The variations are most of the times only a few of the LSB bits. But sometimes the converted value jumps to a completely way off value. After studying the graph you attached, I can see that what happens is that the 0V is measured to a value below zero, hence given a large (over 2.5V) value.

    I've solved the problem by doing several (100) conversions , and then averaging the result.

    May I ask why the ADC outputs a two's complement result? What are the benefits compared to a ''normal'' ADC?

    [ This message was edited by: logic_io-TJ on 18-01-2006 08:58 ]

    Visitor II
    January 18, 2006
    Posted on January 18, 2006 at 05:24

    Hi,

    Normaly there is no big difference betwen a two's complement result and normal result

    But there is a design chose related to the Vref value selection.

    With best regards,

    Hich