BSPI Master Slave Communication

[tevfikyazici]

Posted on November 14, 2006 at 08:27

BSPI Master Slave Communication

[tevfikyazici]

Posted on October 06, 2005 at 13:03

Is there any example code that communicates over bspi.

For examle master: BSPI0 Slave: BSPI1

when we connect pins:

BSPI0.MOSI <-> BSPI1.MOSI

BSPI0.MISO <-> BSPI1.MISO

BSPI0.SCLK <-> BSPI1.SCLK

BSPI0.SSN <-> BSPI1.SSN (is this required)

What should be port configurations for MOSI, MISO, SCLK, SSN for master and slave parts

I write one but it is not working.

________________

Attachments :

bspi_comm.zip : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HtCI&d=%2Fa%2F0X0000000aKD%2FsQMFxwmSRd3kZNjhQD4zV3zROvZ_i94g7.3d14oijjY&asPdf=false

[scanlon]

Posted on October 06, 2005 at 13:56

The difficulty is probably the /ss signal. The master needs to generate a /cs pulse that is active for each transfer (x8 or x16 bit) You cannot use the master /ss signal for this. when the SPI is in master mode, the /ss has some special feature to do with error detection. The /cs pulse (from master to slave /ss) needs to be implemented with a separate gpio pin. Other connections look correct. (didn't look at your code). See reference manual section 11 for more details.

[tevfikyazici]

Posted on October 18, 2005 at 15:22

What should be port configurations for MOSI, MISO, SCLK, SSN for master and slave parts ?

[halim]

Posted on October 19, 2005 at 08:59

Hi,

These pins must be configured in Alternate Function mode

Best regards,

Punto

[ajsndd]

Posted on September 25, 2006 at 03:13

Hello!!

I too have some problems regarding ?BSPI modules in STR71x.

The programme supplied by ST in their site is for BSPI0 master and BSPI1 as slave. and the connection specified is

(S0.MISO)P0.0<-->P0.4(S0.MISO)

(S0.MOSI)P0.1<-->P0.5(S0.MOSI)

(S0.SCLK)P0.2<-->P0.6(S1.SCLK)

(S1.SS)P0.7==GND (what about so.ss???)

BUT WHEN I CHECKED THE CORRESPONDING CONNECTION ON THE DEVELOPMENT BOARD (STD710B)I FOUND IT INCORRECT.ARE THE CONNECTION RIGHT IN THE MENTIONED DEVELOPMENT BOARD.kINDLY REPLY BECAUSE WE ARE STUCK WITH THIS PROBLEM FOR THE PAST 4 DAYS.OUR FURTHER DEVELOPMENT DEPENDS ON ITS SOLUTION.

THANKS 'n' REGARDS

[ajsndd]

Posted on September 29, 2006 at 10:25

So I think the connections for BSPIO0 as master and BSPI1 as slave is surely as below????!!!!

BSPI0.MOSI (P0.1)<-> BSPI1.MOSI (P0.4)

BSPI0.MISO(P0.0) <-> BSPI1.MISO (P0.4)

BSPI0.SCLK(P0.2) <-> BSPI1.SCLK (P0.6)

BSPI1.SSN <--> GND

s0.ss<--> Vcc(+3.3V)

wE ARE USING THE BOARD stdv710b AND THE FLASH IS M25P32...

rEGARDS

ajsndd

[giuseppe2]

Posted on November 09, 2006 at 12:24

Quote:

On 25-09-2006 at 10:38, Anonymous wrote:

The SS pin of the master should be high.

Read the Reference Manual... table 41 and page 236, BERR

Yes ok

But if I don't set ''Alternate Function'' for this pin (p0.7) why not work fine, if i use this for gpio, in master mode ?

tnx Beppe

use: STR71x with raisonance kit